Design of a reversible single precision floating point subtractor
 AV Anantha Lakshmi^{1}Email author and
 GF Sudha^{1}
https://doi.org/10.1186/21931801311
© Anantha Lakshmi and Sudha; licensee Springer. 2014
Received: 11 June 2013
Accepted: 25 December 2013
Published: 4 January 2014
Abstract
In recent years, Reversible logic has emerged as a major area of research due to its ability to reduce the power dissipation which is the main requirement in the low power digital circuit design. It has wide applications like low power CMOS design, Nanotechnology, Digital signal processing, Communication, DNA computing and Optical computing. Floatingpoint operations are needed very frequently in nearly all computing disciplines, and studies have shown floatingpoint addition/subtraction to be the most used floatingpoint operation. However, few designs exist on efficient reversible BCD subtractors but no work on reversible floating point subtractor. In this paper, it is proposed to present an efficient reversible single precision floatingpoint subtractor. The proposed design requires reversible designs of an 8bit and a 24bit comparator unit, an 8bit and a 24bit subtractor, and a normalization unit. For normalization, a 24bit Reversible Leading Zero Detector and a 24bit reversible shift register is implemented to shift the mantissas. To realize a reversible 1bit comparator, in this paper, two new 3x3 reversible gates are proposed The proposed reversible 1bit comparator is better and optimized in terms of the number of reversible gates used, the number of transistor count and the number of garbage outputs. The proposed work is analysed in terms of number of reversible gates, garbage outputs, constant inputs and quantum costs. Using these modules, an efficient design of a reversible single precision floating point subtractor is proposed. Proposed circuits have been simulated using Modelsim and synthesized using Xilinx Virtex5vlx30tff6653. The total onchip power consumed by the proposed 32bit reversible floating point subtractor is 0.410 W.
Keywords
Reversible comparator Reversible floating point subtractor Reversible leading zero detector Reversible shift register Reversible logic FPGAIntroduction

Use minimum number of reversible gates

Use minimum number of garbage outputs

Use minimum constant inputs
The output which cannot be used further for computation process is known as garbage output. The input that is added to an nxk function to make it reversible is called constant input (Thapliyal and Srinivas 2005). The quantum cost of a reversible or quantum circuit is defined as the number of 1 × 1 or 2 × 2 gates used to implement the circuit. The major objective of a reversible logic design is to minimize the quantum cost and the number of garbage outputs (Benett 1998). Hence, one of the major issues in reversible circuit design is garbage minimization to minimise the power dissipation. Another significant criterion in designing a reversible logic circuit is to minimize the number of reversible gates used (Haghparast and Navi 2008). In this paper, it is proposed to design an efficient reversible single precision floating point subtractor. The proposed floating point subtractor design requires an efficient reversible comparator unit, an 8bit and a 24bit reversible subtractor unit, a 24bit reversible leading zero detector unit and a 24bit reversible shift register for normalization. The paper also focuses on the design of a reversible 1bit comparator using the two newly proposed reversible gates Reversible Gate1 (RG1) and Reversible Gate2 (RG2). Since in adiabatic circuits energy is reused rather than just dissipated, the transistor representation of the proposed reversible gates RG1 and RG2 are implemented using adiabatic logic. Also, an eightbit and a 24 –bit reversible comparator is designed using the 1bit comparator. An 8bit and a 24bit reversible subtractor is implemented using the TR gate. Normalization unit requires an efficient reversible leading zero detector and a 24bit reversible shift register. A reversible leading zero detector unit is designed using the Reversible Gate1 (RG1)and a 24bit reversible shift register is implemented using the Fredkin, Feynman and NOT gate. All the proposed circuits have been implemented using VHDL and simulated using Modelsim. The paper is organized as follows: Reversible Logic gates section overviews some of the reversible gates used in the literature. Floating Point Subtraction Algorithm section briefly explains the steps involved in floating point subtraction. Related work section overviews some of the recent relevant methods in the literature. Proposed Reversible gates section introduces the two new reversible gates (RG1 and RG2). Transistor representation of the Proposed Reversible gates using Adiabatic Method section briefly explains the transistor schematic of the proposed gates (RG1 and RG2) using adiabatic logic. Proposed design of Reversible single precision floating point subtractor section explains the efficient realization of 1bit, an 8bit and a 24bit comparator using the two proposed gates RG1 and RG2, realization of an 8bit and a 24bit subtractor using TR gates, realization of a 24bit reversible leading zero detector unit using the proposed gate RG1 and the design of 24bit reversible shift register. Results obtained from the proposed gates are presented in simulation results section. Device utilization summary is presented in synthesis reports section. Finally, Conclusion section summarizes the main conclusions of this work and indicates directions for future work.
Reversible logic gates
Reversible logic gates
SI.No  Gate  Block diagram  Function 

1.  Feynman  P = A  
Q = A ⊕ B  
2.  Toffoli  P = A  
Q = B  
R = AB ⊕ C  
3.  URG  P = (A + B) ⊕ C  
Q = B  
R = AB ⊕ C  
4.  TR  P = A  
Q = A ⊕ B  
R = AB′ ⊕ C  
5.  BJN  P = A  
Q = B  
R = (A + B) ⊕ C  
6.  Fredkin  P = A  
Q = A’B + AC  
R = AB + A’C  
7.  Peres  P = A  
Q = A ⊕ B  
R = AB ⊕ C  
8.  M  P = A  
Q = (A ⊕ B)′  
R = AB′ ⊕ C  
9.  L  P = A  
Q = B  
R = (A + B)′ ⊕ C 
Floating point subtraction algorithm overview
 (1)
Compare the mantissa of the operands.
 (2)
Align binary point:
Initial result exponent: the larger of A_{e}, B_{e}
Compute exponent difference: B_{e}  A_{e}
If B_{e} > = A_{e} Right shift A_{m} that many positions to form A_{m} 2 ^{AeBe}
If A_{e} > B_{e} Right shift B_{m} that many positions to form B_{m} 2 ^{BeAe}
 (3)
Subtract the aligned mantissas: i.e. A_{m}2 ^{AeBe}  B_{m} or A_{m}  B_{m}2 ^{BeAe}
 (4)
If normalization of result is needed, then a normalization step follows:
If ((A_{e} ! = B_{e} and bout = 0) or if A_{e} = B_{e}), then left shift result, decrement result exponent (e.g., if result is 0.001xx…)
Else if A_{e} ! = B_{e} and bout = 1, then Right shift result, increment result exponent (e.g., if result is 10.1xx…) Continue until MSB of data is 1
 (5)
Check result exponent:
If larger than maximum exponent allowed return exponent overflow.
If smaller than minimum exponent allowed return exponent underflow.
From the steps involved in floating point subtraction, the following observations are made: i.
To align the binary point, the initial exponent result should be larger of A_{e}, B_{e}. To realize this, an 8 bit reversible comparator is required to compare the two exponents.
 ii.
To determine A_{e} – B_{e} or B_{e} – A_{e}, an eight bit reversible subtractor is required to be designed.
 iii.
To align the mantissas, A_{m} or B_{m} needs to be shifted for which a 24bit reversible shift register or a 25bit reversible shift register is needed to include the guard bits.
 iv.
To subtract the mantissas, a 24bit reversible subtractor is to be designed.
 v.
To determine the sign part, a 24bit reversible comparator to compare the mantissa is required.
 vi.
For normalization of the result, a 24bit reversible leading zero detector is to be designed.
 i.
Thus the floating point subtraction unit requires the implementation of an 8bit reversible comparator, a 8bit reversible subtractor, a 24bit reversible shift register, a 25bit reversible shift register, a 24bit reversible subtractor, a 24bit reversible comparator and a 24bit reversible leading zero detector.
Related work
A reversible onebit comparator is realized using the existing reversible gates such as Fredkin, Peres, Toffoli, R, URG, TR and the newly proposed gate BJN (Nagamani et al. 2011). The drawback of their work is that the number of reversible gates required for each implementation is more. Also it produces more number of garbage outputs and the circuit uses more number of constant inputs. Another work on reversible one – bit comparator is designed using a single SCG gate (Digantha et al. 2011). The number of garbage outputs produced is 1. It uses 2 constant inputs. The transistor representation of their circuit is not given. Since the logical expressions involved in SCG is complex, definitely it requires more number of transistors to implement. To minimize the transistor count, we have proposed two new 3×3 reversible gates which can be combined for its use as a reversible 1bit comparator. Few works were reported on reversible half subtractors. A reversible half subtractor is realized by Murali (Murali et al. 2002). The drawback of this work is that the critical path delay of a single reversible gate is 4. A work on reversible binary subtractors is carried out using new reversible TR gate (Thapliyal 2011). The number of reversible gates required is one and the critical path delay associated with this circuit is 4. Hence, we have designed a reversible full subtractor using two TR gates. Only few works were reported on reversible sequential elements. A work on reversible D – flipflop contains four New gates and one Feynman gate, a total of 7 reversible gates and produces 8 garbage outputs (Sivakumar et al. 2006). Another work on reversible master–slave Dflipflop is reported by Noor Muhammed Nayeem, Lafifa Jamal and Hafiz Md. Hasan Babu (Noor Muhammed et al. 2009). The number of reversible gates required is 5 and the number of garbage outputs produced by this circuit is 2. The circuit is minimized in terms of gate count and garbage outputs.
Proposed reversible gates (RG1 and RG2)
Proposed Reversible Gate1 (RG1)
Truth table of Reversible Gate 1 (RG1)
A  B  C  P  Q  R 

0  0  0  1  0  0 
0  0  1  1  0  1 
0  1  0  0  0  0 
0  1  1  0  1  1 
1  0  0  1  1  1 
1  0  1  1  1  0 
1  1  0  0  0  1 
1  1  1  0  1  0 
A closer look at the Truth Table reveals that the input pattern corresponding to a specific output pattern can be uniquely determined and thereby maintaining that there is a onetoone correspondence between the input vector and the output vector. In this gate the input vector is given by IV = (A,B,C) and the corresponding output vector is OV = (P,Q,R). The quantum cost of the proposed Reversible Gate1 (RG1) is 5. The quantum cost is calculated based on the number of 1×1 and 2×2 primitive operations.
Proposed Reversible Gate2(RG2)
Truth table of Reversible Gate2 (RG2)
A  B  C  P  Q  R 

0  0  0  1  0  0 
0  0  1  0  0  0 
0  1  0  0  1  0 
0  1  1  1  1  0 
1  0  0  0  1  1 
1  0  1  1  1  1 
1  1  0  0  0  1 
1  1  1  1  0  1 
A closer look at the Truth Table reveals that the input pattern corresponding to a specific output pattern can be uniquely determined and thereby maintaining that there is a onetoone correspondence between the input vector and the output vector. In this gate the input vector is given by IV = (A,B,C) and the corresponding output vector is OV = (P,Q,R). The quantum cost of the proposed Reversible Gate2 (RG2) is 5.
Realization of the classical operations
Proposed Reversible Gate1 (RG1)
Proposed Reversible Gate2 (RG2)
Transistor representation of the proposed reversible gates using adiabatic method
Adiabatic circuits are those circuits which recycles the energy from output nodes instead of discharging it to ground. In literature, adiabatic logic circuits classified into two types: full adiabatic and quasi or partial adiabatic circuits. Fulladiabatic circuits have no nonadiabatic loss, but they are much more complex than quasiadiabatic circuits. Quasiadiabatic circuits have simple architecture and power clock system. There are two types of energy loss in quasiadiabatic circuits, adiabatic loss and nonadiabatic loss. The adiabatic loss occurs when current flows through nonideal switch, which is proportional to the frequency of the powerclock. If any voltage difference between the two terminals of a switch exists when it is turned on, nonadiabatic loss occurs. The nonadiabatic loss, which is independent of the frequency of the powerclock, is proportional to the node capacitance and the square of the voltage difference. Several quasiadiabatic logic architectures have been reported, such as ECRL, 2 N2N2P, PFAL etc. (Athas et al. 1994; Dickinson et al. 1995; Alioto et al. 2001; Fischer et al. 2004; Kime et al. 2005; Anuar et al. 2009; Yadav et al. 2011). In adiabatic systems, more than one power clock is required. We have proposed the transistor representation of the proposed gate Reversible Gate1 and Reversible Gate2 using ECRL technique. In the proposed work, three phases of power clock is used to achieve the synchronization and the input signal is phase shifted by 90° with respect to the power clock.
Transistor representation of proposed Reversible Gate1 (RG1)
If the input B is 0, then the transistor M4 conducts and the output node b will be pulled to logic 0. When the node b is 0, the transistor M1 conducts and the output node bbar follows the clock pulse CLK1. When B is 1, then M3 conducts and the output node bbar will be pulled to logic 0. When the node bbar is 0, the transistor M2 conducts and the output node b follows the clock pulse CLK1. Thus, the transistors M1, M2, M3 and M4 represent the inverter i.e. the function P. The transistors M5, M6, M7, M8, M9, M10, M11, M12, M13 and M14 represent the function ab’ + bc i.e. the function Q. The transistors M15, M16, M17, M18, M20, M21 represent the function a XOR c i.e. the function R. Thus a total of 20 transistors are required to implement the function of Reversible Gate1 using adiabatic logic. The average power dissipated by the gate at a frequency of 50 MHz is 108 mW while the same implementation using CMOS GDI logic dissipates a power of 30 W at a frequency of 50 MHz.
Transistor representation of proposed Reversible Gate2 (RG2)
The transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11 and M12 represent the function (a’b’) XOR c i.e. the function P. The transistors M14, M15, M16 and M17 represent the function of inverter i.e. the function R. The transistors M26, M27, M28, M29, M30, M31, M32 and M33 represent the function a XOR b i.e. the function Q. Thus, a total of 24 transistors are required to implement the Reversible Gate2 using adiabatic logic. The average amount of power dissipated by the proposed implementation at a frequency of 50 MHz is 113 mW while the same implementation using CMOS GDI logic dissipates a power of 40 W at 50 MHz.
Proposed design of reversible single precision floating point subtractor
Realization of onebit comparator
To minimise the transistor count, a reversible onebit comparator is implemented using the proposed reversible Gates1 and 2 (RG1 and RG2).
From reversible Gate1 (RG1), when C is 0, P = B’, R = A and Q = AB’ which represents the greater function. The outputs P and R from reversible gate1 are given as the inputs A and B to the reversible gate2. From reversible gate2 (RG2), when C is 0, P = A’B which represents that A < B, Q = A XNOR B which represents that A = B and R = A which is the garbage output. Thus, the proposed onebit comparator circuit requires 2 reversible gates. The circuit accepts 2 constant inputs and produces one garbage output which is an optimized circuit. The number of transistors required to implement the proposed circuit is 44.
Realization of 8bit comparator
Logic diagram to find the greater of two 8bit numbers

Ei shows True logic when Ai = Bi,

Gi shows True logic when Ai > Bi,
Close observation of (2) reveals that only fourteen reversible gate1 are sufficient to implement the logic, seven working as AND gates and the rest seven as OR gates. It has already been seen in Figures 4 and 5 that a reversible gate1 is capable of implementing the OR operation as well as the AND operation. Figure 14 shows the implementation of (2) for finding out the greater of the two eightbit numbers A and B.
Figure 14 shows the logic diagram for finding the greater of two eightbit numbers.
Number of gates required to find the greater of two eightbit numbers
SI. No  Number of gates required  Number of garbage outputs produced 

1. Proposed work  30  36 
Logic diagram to find the equality of two 8bit numbers
Number of gates required to find the equality of two eightbit numbers
SI. No  Number of gates required  Number of garbage outputs produced 

1. Proposed work  23  22 
Logic diagram to find the smaller of two 8bit numbers
In Figure 16, the signal L will be high when the input A is smaller than B. R1 and R2 represents the garbage output.
Number of gates required to implement an eightbit reversible comparator
SI. No  Number of gates required  Number of garbage outputs produced 

1. Proposed work  26  36 
Realization of 24bit comparator
The two 24bit operands A and B are fed as inputs to 24 onebit comparators. Thus, a reversible 24bit comparator is designed by using twenty four onebit comparators. The twenty four 1bit comparators are used to generate the greater (G0 – G23), equal (E0E23) and the smaller signals (L0L23) of the given two 24bit numbers.
Logical condition for the two 24bit numbers to be equal
To realize this condition, twenty three Reversible Gate1s (RG1) are used to generate the AND term.
Logical condition for finding the greater of two 24bit numbers
To realize Equation 5, twenty three reversible AND gates and twenty three reversible OR gates are required. Reversible AND and OR function is realized using Gate1(RG1)
Logical condition to find the smaller of the two 24bit numbers
Thus the two outputs E and G are fed as the inputs to a reversible gate2.
Number of gates required to implement a 24bit reversible comparator
SI. No  Number of gates required  Number of garbage outputs produced 

1. Proposed work  94  139 
Realization of 8bit subtractor
Number of gates required to implement an eightbit reversible subtractor
SI. No  Number of gates required  Number of garbage outputs produced 

1. Proposed work  15  15 
Thus, the number of gates required to implement an 8bit reversible subtractor is 15.
Realization of reversible 24bit subtractor
Similarly, the reversible 24bit subtractor is designed by cascading a reversible half subtractor and 23 reversible full subtractors.
Number of gates required to implement a 24bit reversible subtractor
SI. No  Number of gates required  Number of garbage outputs produced 

1. Proposed work  47  47 
Thus, the number of gates required to implement a 24bit reversible subtractor is 47.
Proposed design of reversible 24bit leading zero detector
The general procedure for normalization unit of floating point arithmetic is as follows:

Determination of leading zeros

Shifting the resultant fraction (left/right)

Incrementing/Decrementing the exponent based on the shiftoperation

Exception Handling
Hence, a reversible leading zero detector unit is designed using the proposed reversible gate RG1 which detects the number of leading zeros on the mantissa part and then mantissa is shifted leftwise that many number of times. To do so, 23 reversible gates RG1 are cascaded to perform an AND function which determines the all zero case. Based on the AND function output, leading zeros are determined. The output of the arithmetic unit is then shifted to normalize the result (Number of shifts is determined by the zero leading detector), followed by rounding. Thus, the leading zero output is then passed on to the exponent adjustment unit for normalization.
Realization of reversible exponent adjustment unit for normalization
After the subtraction, the result may have a number of leading zero bits or have one more bit with value of one at the most significant bit (MSB). The normalization is needed to adjust the result so that it conforms to the floatingpoint number format. In normalization, if a shift is required, it is either a one place right shift or a multipleplace left shift. If the MSB has a value of one, one place of right shift takes place and the 8bit exponent is passed through a reversible conditional increment unit. To do so, a 25bit reversible right shift register is designed to include the guard bit to yield the correct result. Otherwise, one or several places of left shift is needed in conjunction with a corresponding decrement of the 8bit exponent. Thus, a reversible 8bit Subtractor unit using TR gates is used to adjust the output exponent depending on the number of shifts required. For that, a 24bit reversible leftshift register is designed using the existing reversible Dflipflop to be discussed in the next section.
Realization of 24bit shift register
Comparison of the 24 –bit reversible shift register
No. of gates  Garbage output  

H. Thapliyal and M. Zwolinski (2006)  161  184 
Proposed design  120  49 
Improvement  26%  73% 
It is seen that the proposed design has better performance compared to the existing work. The garbage outputs are 184 in the case of the existing work and 49 in the case of the proposed design i.e., an improvement of 73% in the proposed design compared to the existing work. The number of reversible gates required in the proposed design is 120 while in the case of the existing work is 161i.e an improvement of 26%.
Realization of 25bit right shift register
Number of gates required to implement a 25 –bit reversible shift register
SI. No  Number of gates required  Number of garbage outputs produced 

1. Proposed work  125  51 
Number of gates required for each module of proposed reversible single precision floating point subtractor
Number of gates required  Number of constant inputs  Number of garbage outputs produced  Quantum cost  

24bit subtractor  47  24  47  142 
8bit subtractor  15  8  15  46 
24bit comparator  118  94  163  590 
8bit comparator  34  26  44  170 
24 bit left shift register  120  48  49  312 
25 bit right shift register  125  50  51  325 
24bit leading zero detector  23  23  46  115 
Exponent adjustment unit for normalization (includes 24 8bit subtractors and 24 1bit left shift registers)  475  240  407  1392 
Total  957  513  822  3092 
Simulation results and discussion
The signals a, b, c represents the input signals and p, q, r represents the output signals. From the truth table of reversible gate1 when the inputs a =1,b = 0 and c = 0, the corresponding outputs must be p = 1, q =1 and r = 1 which is depicted in Figure 20.
The signals a, b, c represents the input and p, q, r represents the output. From the truth table of reversible gate2 when the inputs a =1,b = 1 and c = 1, the corresponding outputs must be p = 1, q =0 and r = 1 which is depicted in Figure 21.
The signals a,b,c represents the input and p, q, r represents the output signals where p denotes the greater condition, q represents the smaller condition and r denotes the equality condition. Thus for the input combination a = 0, b = 1 and c = 0, the outputs are p = 0,q = 1 and r = 0. Thus the result indictes that a is smaller than b.
The operands a,b represents the two eightbit numbers and the signals gr,eq and lt represents the output signals to indicate the greater, equality and lesser condition. For the input a = 10001101, b = 10001101, the outputs are gr = 0, eq = 1 and lt = 0. Thus the simulation result indicates that a is equal to b.
The operands a,b represents the two eightbit numbers, cin is the primary carry/borrow input signal and the signals d, bo represents the eightbit difference and borrow signals, bout is the primary borrowout signal. For the input a = 00010000, b = 00000100, d = 00001100, bout = 0. Thus the simulation result depicts the implementation of eightbit subtractor.
The operands a,b represents the two 24bit numbers, cin is the primary carry/borrow input signal and the signals d, bo represents the 24bit difference and borrow signals, bout is the primary borrowout signal. For the input a = 110010001100101011011010 b = 001011000010101011010010, d = 100111001010000000001000, bout = 0. Thus the simulation result depicts the implementation of 24bit subtractor.
The operand a represents the 24bit number to be shifted, clk is the primary clock signal and the signal ×1 represents the 24bit shifted output. For the input a = 110010101010110011011010, ×1 = 011001010101011001101101 which is the shifted output of the signal a.
The operands a and b represents the two 32bit floating point numbers. The signals gr,lt and eq represents the greater, smaller and equal conditions of a reversible eightbit comparator. The signals gr1,lt1 and eq1 represents the greater, smaller and equal conditions of the reversible 24bit comparator. The signals shift1 and shift2 represents the shifted versions of the mantissas a and b.
The signal d represents the 32bit floating point subtractor result.
Synthesis report
The entire design has been synthesized using Xilinx Virtex5vlx30tff6653. Each module is implemented using dataflow style of modelling. Then the top design is implemented using structural style of modelling.
Device utilization summary of the reversible single precision floating point subtractor
Device utilization summary (estimated values)  

Logic utilization  Used  Available  Utilization 
Number of slice registers  97  19200  0% 
Number of slice LUTs  698  19200  3% 
Number of fully used LUTFF pairs  97  698  13% 
Number of bonded IOBs  100  360  27% 
Number of BUFG/BUFGCTRLs  3  32  9% 
Power consumption of the proposed work
The total onchip power consumed by the proposed 32bit reversible floating point subtractor is 0.410 W.
Conclusion
In this paper, an efficient reversible single precision floating point subtractor is designed with lesser number of garbage outputs, constant inputs and minimum number of transistors and has a latency of 2 clock cycles. An 8bit and 24bit reversible comparator is designed using the optimized 1bit comparator with the reversible gates Reversible Gate1 and Reversible Gate2. An eightbit and 24bit reversible subtractor is designed using TR gates with less critical path delay. A 24bit and a 25bit reversible shift register is designed using the existing Dflipflop and a 24bit Reversible Leading Zero detector is designed using our proposed gate RG1. In effect, an efficient reversible single precision floating point subtractor is designed which will be very useful for the future computing techniques like ultra low power digital circuits and quantum computers. It is shown that the proposal is highly optimized in terms of number of reversible logic gates, number of garbage outputs, number of constant inputs and quantum cost. The future work is to use the proposed work in the design of reversible single precision floating point divider.
Declarations
Authors’ Affiliations
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