Table 10 Comparison of the 24 –bit reversible shift register
From: Design of a reversible single precision floating point subtractor
No. of gates | Garbage output | |
|---|---|---|
H. Thapliyal and M. Zwolinski (2006) | 161 | 184 |
Proposed design | 120 | 49 |
Improvement | 26% | 73% |
From: Design of a reversible single precision floating point subtractor
No. of gates | Garbage output | |
|---|---|---|
H. Thapliyal and M. Zwolinski (2006) | 161 | 184 |
Proposed design | 120 | 49 |
Improvement | 26% | 73% |