Table 11 Number of gates required to implement a 25 –bit reversible shift register
From: Design of a reversible single precision floating point subtractor
SI. No | Number of gates required | Number of garbage outputs produced |
|---|---|---|
1. Proposed work | 125 | 51 |
From: Design of a reversible single precision floating point subtractor
SI. No | Number of gates required | Number of garbage outputs produced |
|---|---|---|
1. Proposed work | 125 | 51 |