Table 12 Number of gates required for each module of proposed reversible single precision floating point subtractor
From: Design of a reversible single precision floating point subtractor
Number of gates required | Number of constant inputs | Number of garbage outputs produced | Quantum cost | |
|---|---|---|---|---|
24-bit subtractor | 47 | 24 | 47 | 142 |
8-bit subtractor | 15 | 8 | 15 | 46 |
24-bit comparator | 118 | 94 | 163 | 590 |
8-bit comparator | 34 | 26 | 44 | 170 |
24- bit left shift register | 120 | 48 | 49 | 312 |
25- bit right shift register | 125 | 50 | 51 | 325 |
24-bit leading zero detector | 23 | 23 | 46 | 115 |
Exponent adjustment unit for normalization (includes 24 8-bit subtractors and 24 1-bit left shift registers) | 475 | 240 | 407 | 1392 |
Total | 957 | 513 | 822 | 3092 |