Open Access

Design and implementation of an efficient single layer five input majority voter gate in quantum-dot cellular automata


Received: 18 October 2015

Accepted: 22 April 2016

Published: 17 May 2016


The fundamental logical element of a quantum-dot cellular automata (QCA) circuit is majority voter gate (MV). The efficiency of a QCA circuit is depends on the efficiency of the MV. This paper presents an efficient single layer five-input majority voter gate (MV5). The structure of proposed MV5 is very simple and easy to implement in any logical circuit. This proposed MV5 reduce number of cells and use conventional QCA cells. However, using MV5 a multilayer 1-bit full-adder (FA) is designed. The functional accuracy of the proposed MV5 and FA are confirmed by QCADesigner a well-known QCA layout design and verification tools. Furthermore, the power dissipation of proposed circuits are estimated, which shows that those circuits dissipate extremely small amount of energy and suitable for reversible computing. The simulation outcomes demonstrate the superiority of the proposed circuit.


Quantum-dot cellular automata (QCA) Five-input majority gate (MV5) QCA full-adder (FA) QCADesigner Expandable MV


Now a day’s, CMOS technology is approaching its physical boundary and facing earnest challenges by designing perpetually incrementing frequencies and downscaling of computational devices. This technology has found many complication like high leakage current, high power consumption, high lithography cost, low density problem and limitation of speed in GHz range. Therefore, to overcome the deficiencies an extensive research on nanotechnologies must be taken into consideration. A report of ITRS (International Technology Road 2013) shows a road map of future computing technologies. Quantum-dot cellular automata (Lent et al. 1993; Orlov et al. 1997) is one of the promising alternative technologies that proffers an innovative approach and has exhibited ultra low power, extreme speed and highly dense digital devise designing capabilities. In addition, QCA based memory unit, reversible logic and arithmetic logic circuit have been considered in several studies (Kim et al. 2007; Navi et al. 2010; Hänninen and Takala 2010; Hashemi et al. 2012; Qanbari and Sabbaghi-Nadooshan 2013; Kianpour and Sabbaghi-Nadooshan 2014; Sayedsalehi et al. 2015; Angizi et al. 2015; Bahar et al. 2015).

The rudimentary element of QCA circuit is a majority gate (MV); digital operation can be employed by using MV. MV characterizes and determines the function value based on majority verdict (Oya et al. 2003). Up to now, most QCA circuits have been investigated and designed only by means of 3-input majority gates (MV3). However, if these circuits are constructed using 5-input majority gates (MV5), they would be optimized in cell counts, area and complexity.

To reveal the effectiveness of proposed MV5, a QCA full-adder has been designed using proposed MV5. Results reveal the superiority of proposed FA in terms of latency, cell counts and area to other previous designs (Tougaw and Lent 1994; Wang et al. 2003; Zhang et al. 2004; Azghadi et al. 2007; Cho and Swartzlander 2007, 2009).

Proposed five-input majority gate

MV5 is a cell arrangement which includes five input cells, one output and some device cells. The logic function of MV5 can be presented as Eq. (1), where the inputs are labeled as A, B, C, D and E respectively. The truth table of the MV5 is shown in Table 1.
Table 1

Truth table of MV5 based on sum of inputs

Σ (A, B, C, D, E)

MV (A, B, C, D, E)













$$MV \left( {A, B, C, D, E} \right) = ABC\,+\,ABD\,+\,ABE\,+\,ACD\,+\,ACE\,+\,ADE\,+\,BCD\,+\,BCE\,+\,BDE\,+\,CDE$$
The proposed design of MV5 is shown in Fig. 1. In this design, A, B, C, D and E are labeled as inputs and the output cell is labeled as OUTPUT. Additionally, three middle cells are labeled 1, 2 and 3. Polarization of input cells are fixed and middle cells and output cell are free to change. Here, cell “A” has an impact on all the middle cells. Similarly, cell “B”, cell “C” cell “D” and cell “E” also have an impact on all the middle cells. These impacts are propagated to the output cell and construct the MV5 output, efficiently. The propose MV5 requires only nine cells and uses conventional QCA cells to implement.
Fig. 1

Proposed 5-input majority gate

Physical proofs

To carry out the physical proofs, the below postulates are considered:
  • All cells are alike and the distance of end to end of each cell is 18 nm.

  • The space between two neighbor cells is 2 nm shown in Fig. 2.
    Fig. 2

    Two rectangular QCA cell

The proposed MV5 has approximately 32 distinct input states; we should verify all the input condition to validate the accuracy of the gate. In this paper, only one state (A = 1, B = 0, C = D = E = 1) has been considered for verification. Similarly, other states can be verified too. For a fixed input MV5, the five input cells polarization are remain unchanged; only the intermediary cells and the output cell are subject to be changed to their polarization according to the input cells. Here, the proposed MV5 have three intermediary cells and one output cell those are labeled as 1, 2, 3 and OUTPUT respectively shown in Fig. 1.

A structure is said to be stable, when the QCA cells are assembled with their minimum potential energies. The potential energy between two different cell electrons can be computed using the Eq. (2) (Halliday and Resnick 2004; McDermott 1984; Halloun and Hestenes 1985). Here, U is potential energy; a fixed colon is k, q 1 and q 2 are electric charges, and the distance between two electric charges is r. The total potential energy of a given structure is “U T ” and that can be calculated using Eq. (3).
$$U = \frac{{kq_{1} q_{2} }}{r}$$
$$U_{T} = \mathop \sum \limits_{i = 1}^{n} U_{i}$$
For, finding the stable structure, one needs to calculate the potential energy U i for each middle cell. Here, cell 1 has two different polarization state; polarization P = +1 and P = −1 shown in Fig. 3.
Fig. 3

Five-input majority gate a cell-1 polarization P = −1, b cell-1 polarization P = +1

Now, considering state 3 (a); here the potential energy for cell 1 U T is the summation of potential energies of both x and y electrons. Potential energy for x and y electrons are the total energy exist between each electron (e 1, e 2, e 3, e 4, e 5, e 6, e 7, e 8 , e 9 , and e 10) with electron x and y respectively, which is calculated using Eq. (2). Finally, using Eq. (3) total potential energy for “cell 1” can be calculated. Similarly, potential energy of “cell 1” for state 3.3 (b) can be calculated. The necessary calculations for finding the total potential energies of structure (a) and structure (b) are given below:

Figure 3a (For electron x)

Figure 3a (For electron y)

\(U_{1} = \frac{A}{{r_{1} }} = \frac{{23.04 \times 10^{ - 29} }}{{20 \times 10^{ - 9} }} \approx 1.15 \times 10^{ - 20} J\)

\(U_{2} = \frac{A}{{r_{2} }} = \frac{{23.04 \times 10^{ - 29} }}{{18.11 \times 10^{ - 9} }} \approx 1.27 \times 10^{ - 20} J\)

\(U_{3} = \frac{A}{{r_{3} }} = \frac{{23.04 \times 10^{ - 29} }}{{2 \times 10^{ - 9} }} \approx 11.52 \times 10^{ - 20} J\)

\(U_{4} = \frac{A}{{r_{4} }} = \frac{{23.04 \times 10^{ - 29} }}{{26.91 \times 10^{ - 9} }} \approx 0.86 \times 10^{ - 20} J\)

\(U_{5} = \frac{A}{{r_{5} }} = \frac{{23.04 \times 10^{ - 29} }}{{20 \times 10^{ - 9} }} \approx 1.15 \times 10^{ - 20} J\)

\(U_{6} = \frac{A}{{r_{6} }} = \frac{{23.04 \times 10^{ - 29} }}{{42.04 \times 10^{ - 9} }} \approx 0.55 \times 10^{ - 20} J\)

\(U_{7} = \frac{A}{{r_{7} }} = \frac{{23.04 \times 10^{ - 29} }}{{44.72 \times 10^{ - 9} }} \approx 0.52 \times 10^{ - 20} J\)

\(U_{8} = \frac{A}{{r_{8} }} = \frac{{23.04 \times 10^{ - 29} }}{{43.91 \times 10^{ - 9} }} \approx 0.53 \times 10^{ - 20} J\)

\(U_{9} = \frac{A}{{r_{9} }} = \frac{{23.04 \times 10^{ - 29} }}{{44.72 \times 10^{ - 9} }} \approx 0.52 \times 10^{ - 20} J\)

\(U_{10} = \frac{A}{{r_{10} }} = \frac{{23.04 \times 10^{ - 29} }}{{69.34 \times 10^{ - 9} }} \approx 0.33 \times 10^{ - 20} J\)

\(U_{{T_{{}} x_{1} }}^{ - } = \sum\nolimits_{i = 1}^{10} {U_{i} } = 18.38 \times 10^{ - 20} J\)

\(U_{1} = \frac{A}{{r_{1} }} = \frac{{23.04 \times 10^{ - 29} }}{{42.04 \times 10^{ - 9} }} \approx 0.55 \times 10^{ - 20} J\)

\(U_{2} = \frac{A}{{r_{2} }} = \frac{{23.04 \times 10^{ - 29} }}{{20 \times 10^{ - 9} }} \approx 1.15 \times 10^{ - 20} J\)

\(U_{3} = \frac{A}{{r_{3} }} = \frac{{23.04 \times 10^{ - 29} }}{{26.91 \times 10^{ - 9} }} \approx 0.86 \times 10^{ - 20} J\)

\(U_{4} = \frac{A}{{r_{4} }} = \frac{{23.04 \times 10^{ - 29} }}{{38 \times 10^{ - 9} }} \approx 0.61 \times 10^{ - 20} J\)

\(U_{5} = \frac{A}{{r_{5} }} = \frac{{23.04 \times 10^{ - 29} }}{{18.11 \times 10^{ - 9} }} \approx 1.27 \times 10^{ - 20} J\)

\(U_{6} = \frac{A}{{r_{6} }} = \frac{{23.04 \times 10^{ - 29} }}{{20 \times 10^{ - 9} }} \approx 1.15 \times 10^{ - 20} J\)

\(U_{7} = \frac{A}{{r_{7} }} = \frac{{23.04 \times 10^{ - 29} }}{{58.03 \times 10^{ - 9} }} \approx 0.40 \times 10^{ - 20} J\)

\(U_{8} = \frac{A}{{r_{8} }} = \frac{{23.04 \times 10^{ - 29} }}{{44.72 \times 10^{ - 9} }} \approx 0.52 \times 10^{ - 20} J\)

\(U_{9} = \frac{A}{{r_{9} }} = \frac{{23.04 \times 10^{ - 29} }}{{22.09 \times 10^{ - 9} }} \approx 1.04 \times 10^{ - 20} J\)

\(U_{10} = \frac{A}{{r_{10} }} = \frac{{23.04 \times 10^{ - 29} }}{{44.72 \times 10^{ - 9} }} \approx 0.52 \times 10^{ - 20} J\)

\(U_{{T_{{y_{1} }} }}^{ - } = \sum\nolimits_{i = 1}^{10} {U_{i} } = 8.05 \times 10^{ - 20} J\)

Total potential energy of Fig. 3a is
$$U_{{T_{1} }}^{ - } = 26.42 \times 10^{ - 20} J$$
Similarly, the total potential energy for Fig. 3b can be calculated and it is
$$U_{{T_{1} }}^{ + } = 36.33 \times 10^{ - 20} J$$
With comparison of the achieved results, the electrons in cell 1 are located in state (a) is more stable because it has the lower potential energy than state (b). Similar the potential energy for cell 2 and cell 3 can be calculated and the final results are mentioned as.
$$U_{{_{2} }}^{ - } = 23.39 \times 10^{ - 20} J\quad U_{{T_{2} }}^{ + } = 23.86 \times 10^{ - 20} J$$
$$U_{{T_{3} }}^{ - } = 14.35 \times 10^{ - 20} J\quad U_{{T_{3} }}^{ + } = 33.38 \times 10^{ - 20} J$$

Proposed QCA full-adder

The proposed MV5 is implemented by designing an efficient QCA full-adder. The schematic diagram of newly proposed QCA full-adder is shown in Fig. 4.
Fig. 4

Schematic diagram of QCA full-adder

This full-adder is designed using the planar designing concept. The proposed FA has been implemented using 2-inverters and 2-MVs. In comparison with the earlier FA (Azghadi et al. 2007), it has an extra inverter gate. The structure of proposed MV5, it would be easier to employ 2-inverters rather than 1-inverter and some wires for transmitting the inverted signal to other part. The proposed QCA FA is simple in structure and easy to construct. In this design, at first the carry value is calculated and then takes its inversion value and uses this value as an input of the MV5 gates.

Power dissipation of proposed QCA full-adder

The power dissipates from a single cell depends on the rate of change of the clock and the tunneling energy. The power dissipation of a QCA circuit in a single clock phase can be simply calculated by adding the power dissipated by each majority gate and inverter (Liu et al. 2012).

Using Hamming distance (HD) power dissipation of a QCA circuit can be estimated. Power dissipation is depends on HD between input cells to inverter cells as well as HD between majority voter gates (Liu et al. 2012). For an inverter when the input is changed from 0 → 0 or 1 → 1. In this case the HD will be 0, and the power dissipation by inverter at γ = 0.25 E k and T = 2.0 K is 0.8 meV whereas for γ = 1.0 E k , it is 8.0 meV (Liu et al. 2012). If the input is changed from 0 → 1 or 1 → 0, in this case the HD will be 1 and the power dissipation by the inverter is 28.4 meV, where T = 2.0 K and γ = 0.25 E k . For majority gate, power dissipation is minimum, when the inputs are changed from 000 → 000 i.e. HD is 0, and the power dissipation is maximum when polarization of all inputs are changed i.e. input polarization are changed from 000 → 111 i.e. HD is 3. The power dissipation by the majority voter gate for HD 0 and 3 are 0.8 and 41.0 meV respectively, where γ = 0.25 E k and T = 2.0 K (Liu et al. 2012).

By using Hamming distance based methodology described in (Liu et al. 2012), the power dissipated by the proposed MV5 and 1-bit QCA full-adder is estimated and the results are shown in Table 2.
Table 2

Power dissipation of proposed five input majority gate and QCA full adder


Power dissipation at T = 2.0 K

γ = 0.25 E k (meV)

γ = 0.50 E k (meV)

γ = 0.75 E k (meV)

γ = 1.0 E k (meV)

Five input majority gate





QCA full-adder





Simulations and results comparison

The proposed MV5 and FA have been simulated and verified using QCADesigner (Walus et al. 2003, 2004) only tools for QCA layout design and verification. In these simulations, both bi-stable and coherence vector engines have been employed to simulate. In both simulations identical outputs are obtained which confirm the correctness of the proposed designs. The simulated circuit layout and simulated output of proposed MV5 are shown in Fig. 5.
Fig. 5

Simulated a circuit layout and b input–output wave form of proposed MV5

The proposed QCA full-adder is designed in three layers illustrated in Fig. 6. The main layer contains 34 cells, second layer contains 4 cells and the third layer contains 10 cells. Finally, it requires 48 cells and 3 clock phases to produce exact outputs (Sum and Carry).
Fig. 6

Simulated circuit layout of proposed full-adder a main layer, b layer-1, c layer-2, d top view of the adder, e simulation result

Using QCADesigner, complexity, time delay and area consumption of QCA circuits can easily be calculated (Walus et al. 2003). Table 3 demonstrates a concise comparison between the proposed QCA FA and the earlier FA (Vetteth et al. 2002; Wang et al. 2003; Zhang et al. 2005; Cho and Swartzlander 2007; Kim et al. 2007; Cho and Swartzlander 2007, 2009; Navi et al. 2010; Hänninen and Takala 2010; Hashemi et al. 2012; Qanbari and Sabbaghi-Nadooshan 2013) in terms of complexity, area and time delay. Here, complexity indicates the number of cell is used to design the FA. Similarly, the area represents the total covered area of the corresponding FA in micro meter. The “Latency” indicates the number of clock zone used. It also indicates the time delay of the circuit.
Table 3

Comparison of QCA full-adders in terms of gate count, area and latency

Full adder

Type of full adder

Complexity (cells)

Area (μm2)

Latency (clock cycle)

FA [1]

Coplanar QCA FA (Vetteth et al. 2002)




FA [2]

Robust QCA FA (Kim et al. 2007)




FA [3]

Coplanar QCA FA (Wang et al. 2003)




FA [4]

Type-I QCA FA (Cho and Swartzlander 2007)




FA [5]

Multilayer QCA FA (Zhang et al. 2005)




FA [6]

The Robust QCA FA (Hänninen and Takala 2010)




FA [7]

Type-II QCA FA (Cho 2006; Azghadi et al. 2007)




FA [8]

Robust QCA FA (Hashemi et al. 2012)




FA [9]

Multilayer QCA FA (Navi et al. 2010)




FA [10]

Multilayer QCA FA (Qanbari and Sabbaghi-Nadooshan 2013)





Proposed full adder




It is clear that the new QCA full-adder dominates all the previous designs (Vetteth et al. 2002; Wang et al. 2003; Zhang et al. 2005; Cho and Swartzlander 2007; Kim et al. 2007; Cho and Swartzlander 2007, 2009; Navi et al. 2010; Hänninen and Takala 2010; Hashemi et al. 2012; Qanbari and Sabbaghi-Nadooshan 2013) in terms of covered area and number of cell count. It leads to a very dense structure and has the same time delay with the previous best designs (Qanbari and Sabbaghi-Nadooshan 2013). According to the bar chat shown in Fig. 7, the proposed FA leads to around 95.17 % improvement in area and 83.6 percent improvement in cell complexity in comparison to the QCA FA designed using 3-input majority gates and inverters in (Vetteth et al. 2002). This FA also, leads to around 40 % improvement in area and 23.8 % improvement in cell complexity compared to the best QCA FA designed using previous MV5 and inverters (Qanbari and Sabbaghi-Nadooshan 2013).
Fig. 7

A comparative analysis of proposed full-adder with previous

Reliability of proposed QCA circuits

The temperature effect on the output cell’s polarization of proposed MV5 and QCA FA are observed. The output cell’s polarization is taken at different temperature using QCADesigner tool. The average output polarization (AOP) for each output cell is calculated from (Pudi and Sridharan 2011) and shown in Fig. 8. The proposed circuit works efficiently in temperature range of 1–6 K, and the AOP for each output cell is changed very little in this range. When the temperature is above 6 K, the AOP is dropped drastically, which results incorrect outputs.
Fig. 8

The effect of temperature on average output polarization (AOP) of proposed MV5 and QCA FA


A new flexible 5-input majority gate and a new efficient full-adder have been presented. The proposed MV5 has been implemented in one layer and using nine QCA cells only. To validate the correctness and effectiveness of the proposed MV5 a QCA FA has been presented. Moreover the estimation of power dissipation by the proposed QCA full-adder circuits illustrates that the proposed QCA FA is highly energy efficient circuit. The proposed FA has a considerable improvement in comparison to the previous FAs in terms of covered area, number of cells and has a similar time delay to the previous best FA.


Authors’ contributions

ANB designed the logic of proposed circuits and simulated them using QCADesigner. SW helped to calculate the power dissipation and temperature effect on AOP of proposed circuits. All authors read and approved the final manuscript.


We express our thanks to NH, Nazir Hossain, for his valuable guideline in preparing manuscript.

Competing interests

Both authors declare that they have no competing interests.

Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (, which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Authors’ Affiliations

Department of Information and Communication Technology, Mawlana Bhashani Science and Technology University


  1. Angizi S, Moaiyeri MH, Farrokhi S, Navi K, Bagherzadeh N (2015) Designing quantum-dot cellular automata counters with energy consumption analysis. Microprocess Microsyst 39(7):512–520View ArticleGoogle Scholar
  2. Azghadi MR, Kavehei O, Navi K (2007) A novel design for quantum-dot cellular automata cells and full adders. J Appl Sci 7(22):3460–3468View ArticleGoogle Scholar
  3. Bahar AN, Waheed S, Hossain N (2015) A new approach of presenting reversible logic gate in nanoscale. SpringerPlus 4(1):153View ArticleGoogle Scholar
  4. Cho H (2006) Adder and multiplier design and analysis in quantum-dot cellular automata. PhD dissertation, Faculty of the Graduate School, University of Texas, AustinGoogle Scholar
  5. Cho H, Swartzlander EE (2007) Adder designs and analyses for quantum-dot cellular automata. IEEE Trans Nanotechnol 6(3):374–383View ArticleGoogle Scholar
  6. Cho H, Swartzlander EE (2009) Adder and multiplier design in quantum-dot cellular automata. IEEE Trans Comput 58(6):721–727View ArticleGoogle Scholar
  7. Halliday D, Resnick A (2004) Fundamentals of physics, part 1, chapters 3–6, 7th edn. Wiley, New YorkGoogle Scholar
  8. Halloun IA, Hestenes D (1985) Common sense concepts about motion. Am J Phys 53(11):1056–1065View ArticleGoogle Scholar
  9. Hänninen I, Takala J (2010) Binary adders on quantum-dot cellular automata. Sci J Circ Syst Signal Process 58(1):87–103View ArticleGoogle Scholar
  10. Hashemi S, Tehrani M, Navi K (2012) An efficient quantum-dot cellular automata full-adder. Sci Res Essays 7(2):177–189Google Scholar
  11. International Technology Road map for Semiconductors (ITRS) (2013) International Roadmap Committee. Accessed 11 Oct 2015
  12. Kianpour M, Sabbaghi-Nadooshan R (2014) A conventional design and simulation for CLB implementation of an FPGA quantum-dot cellular automata. Microprocess Microsyst 38(8):1046–1062View ArticleGoogle Scholar
  13. Kim K, Wu K, Karri R (2007) The robust QCA adder designs using composable QCA building blocks. IEEE Trans Comput Aided Des Integr Circ Syst 26(1):176–183View ArticleGoogle Scholar
  14. Lent CS, Tougaw PD, Porod W (1993) Bistable saturation in coupled quantum dots for quantum cellular automata. Appl Phys Lett 62(7):714–716View ArticleGoogle Scholar
  15. Liu W, Srivastava S, Lu L, O’Neill M, Swartzlander EE Jr (2012) Are QCA cryptographic circuits resistant to power analysis attack? IEEE Trans Nanotechnol 11(6):1239–1251View ArticleGoogle Scholar
  16. McDermott LC (1984) Research on conceptual understanding in mechanics. Phys Today 37(7):24–32View ArticleGoogle Scholar
  17. Navi K, Farazkish R, Sayedsalehi S, Azghadi MR (2010) A new quantum-dot cellular automata full-adder. Microelectr J 41(12):820–826View ArticleGoogle Scholar
  18. Orlov A, Amlani I, Bernstein G, Lent C, Snider G (1997) Realization of a functional cell for quantum-dot cellular automata. Science 277(5328):928–930View ArticleGoogle Scholar
  19. Oya T, Asai T, Fukui T, Amemiya Y (2003) A majority-logic device using an irreversible single-electron box. IEEE Trans Nanotechnol 2(1):15–22View ArticleGoogle Scholar
  20. Pudi V, Sridharan K (2011) Efficient design of a hybrid adder in quantum-dot cellular automata. IEEE Trans Very Large Scale Integr Syst 19(9):1535–1548View ArticleGoogle Scholar
  21. Qanbari M, Sabbaghi-Nadooshan R (2013) Two Novel quantum-dot cellular automata full adders. J Eng 2013:6View ArticleGoogle Scholar
  22. Sayedsalehi S, Azghadi MR, Angizi S, Navi K (2015) Restoring and non-restoring array divider designs in quantum-dot cellular automata. Inf Sci 311:86–101View ArticleGoogle Scholar
  23. Tougaw PD, Lent CS (1994) Logical devices implemented using quantum cellular automata. J Appl Phys 75(3):1818–1825View ArticleGoogle Scholar
  24. Vetteth A, Walus K, Dimitrov VS, Jullien GA (2002) Quantum-dot cellular automata carry-look-ahead adder and barrel shifter. In: IEEE Emerging Telecommunications Technologies Conference 2–4Google Scholar
  25. Walus K, Dimitrov V, Jullien GA, Miller WC (2003) QCADesigner: a CAD tool for an emerging nano-technology. In: Micronet Annual Workshop, pp 292–294Google Scholar
  26. Walus K, Dysart TJ, Jullien GA, Budiman RA (2004) QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata. IEEE Trans Nanotechnol 3(1):26–31View ArticleGoogle Scholar
  27. Wang W, Walus K, Jullien GA (2003) Quantum-dot cellular automata adders. In: 2003 third IEEE conference on nanotechnology, NANO 2003, IEEE, vol 1, pp 461–464Google Scholar
  28. Zhang R, Walus K, Wang W, Jullien GA (2004) A method of majority logic reduction for quantum cellular automata. IEEE Trans Nanotechnol 3(4):443–450View ArticleGoogle Scholar
  29. Zhang R, Walus K, Wang W, Jullien GA (2005) Performance comparison of quantum-dot cellular automata adders. In: IEEE international symposium on circuits and systems, ISCAS 2005, IEEE, vol 03, pp 2522–2526Google Scholar


© The Author(s). 2016