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Design and implementation of an efficient single layer five input majority voter gate in quantumdot cellular automata
 Ali Newaz Bahar^{1}Email author and
 Sajjad Waheed^{1}
 Received: 18 October 2015
 Accepted: 22 April 2016
 Published: 17 May 2016
Abstract
The fundamental logical element of a quantumdot cellular automata (QCA) circuit is majority voter gate (MV). The efficiency of a QCA circuit is depends on the efficiency of the MV. This paper presents an efficient single layer fiveinput majority voter gate (MV_{5}). The structure of proposed MV_{5} is very simple and easy to implement in any logical circuit. This proposed MV_{5} reduce number of cells and use conventional QCA cells. However, using MV_{5} a multilayer 1bit fulladder (FA) is designed. The functional accuracy of the proposed MV_{5} and FA are confirmed by QCADesigner a wellknown QCA layout design and verification tools. Furthermore, the power dissipation of proposed circuits are estimated, which shows that those circuits dissipate extremely small amount of energy and suitable for reversible computing. The simulation outcomes demonstrate the superiority of the proposed circuit.
Keywords
 Quantumdot cellular automata (QCA)
 Fiveinput majority gate (MV_{5})
 QCA fulladder (FA)
 QCADesigner
 Expandable MV
Background
Now a day’s, CMOS technology is approaching its physical boundary and facing earnest challenges by designing perpetually incrementing frequencies and downscaling of computational devices. This technology has found many complication like high leakage current, high power consumption, high lithography cost, low density problem and limitation of speed in GHz range. Therefore, to overcome the deficiencies an extensive research on nanotechnologies must be taken into consideration. A report of ITRS (International Technology Road 2013) shows a road map of future computing technologies. Quantumdot cellular automata (Lent et al. 1993; Orlov et al. 1997) is one of the promising alternative technologies that proffers an innovative approach and has exhibited ultra low power, extreme speed and highly dense digital devise designing capabilities. In addition, QCA based memory unit, reversible logic and arithmetic logic circuit have been considered in several studies (Kim et al. 2007; Navi et al. 2010; Hänninen and Takala 2010; Hashemi et al. 2012; Qanbari and SabbaghiNadooshan 2013; Kianpour and SabbaghiNadooshan 2014; Sayedsalehi et al. 2015; Angizi et al. 2015; Bahar et al. 2015).
The rudimentary element of QCA circuit is a majority gate (MV); digital operation can be employed by using MV. MV characterizes and determines the function value based on majority verdict (Oya et al. 2003). Up to now, most QCA circuits have been investigated and designed only by means of 3input majority gates (MV_{3}). However, if these circuits are constructed using 5input majority gates (MV_{5}), they would be optimized in cell counts, area and complexity.
To reveal the effectiveness of proposed MV_{5}, a QCA fulladder has been designed using proposed MV_{5}. Results reveal the superiority of proposed FA in terms of latency, cell counts and area to other previous designs (Tougaw and Lent 1994; Wang et al. 2003; Zhang et al. 2004; Azghadi et al. 2007; Cho and Swartzlander 2007, 2009).
Proposed fiveinput majority gate
Truth table of MV_{5} based on sum of inputs
Σ (A, B, C, D, E)  MV (A, B, C, D, E) 

0  0 
1  0 
2  0 
3  1 
4  1 
5  1 
Physical proofs

All cells are alike and the distance of end to end of each cell is 18 nm.

The space between two neighbor cells is 2 nm shown in Fig. 2.
The proposed MV_{5} has approximately 32 distinct input states; we should verify all the input condition to validate the accuracy of the gate. In this paper, only one state (A = 1, B = 0, C = D = E = 1) has been considered for verification. Similarly, other states can be verified too. For a fixed input MV_{5}, the five input cells polarization are remain unchanged; only the intermediary cells and the output cell are subject to be changed to their polarization according to the input cells. Here, the proposed MV_{5} have three intermediary cells and one output cell those are labeled as 1, 2, 3 and OUTPUT respectively shown in Fig. 1.
Figure 3a (For electron x)  Figure 3a (For electron y) 

\(U_{1} = \frac{A}{{r_{1} }} = \frac{{23.04 \times 10^{  29} }}{{20 \times 10^{  9} }} \approx 1.15 \times 10^{  20} J\) \(U_{2} = \frac{A}{{r_{2} }} = \frac{{23.04 \times 10^{  29} }}{{18.11 \times 10^{  9} }} \approx 1.27 \times 10^{  20} J\) \(U_{3} = \frac{A}{{r_{3} }} = \frac{{23.04 \times 10^{  29} }}{{2 \times 10^{  9} }} \approx 11.52 \times 10^{  20} J\) \(U_{4} = \frac{A}{{r_{4} }} = \frac{{23.04 \times 10^{  29} }}{{26.91 \times 10^{  9} }} \approx 0.86 \times 10^{  20} J\) \(U_{5} = \frac{A}{{r_{5} }} = \frac{{23.04 \times 10^{  29} }}{{20 \times 10^{  9} }} \approx 1.15 \times 10^{  20} J\) \(U_{6} = \frac{A}{{r_{6} }} = \frac{{23.04 \times 10^{  29} }}{{42.04 \times 10^{  9} }} \approx 0.55 \times 10^{  20} J\) \(U_{7} = \frac{A}{{r_{7} }} = \frac{{23.04 \times 10^{  29} }}{{44.72 \times 10^{  9} }} \approx 0.52 \times 10^{  20} J\) \(U_{8} = \frac{A}{{r_{8} }} = \frac{{23.04 \times 10^{  29} }}{{43.91 \times 10^{  9} }} \approx 0.53 \times 10^{  20} J\) \(U_{9} = \frac{A}{{r_{9} }} = \frac{{23.04 \times 10^{  29} }}{{44.72 \times 10^{  9} }} \approx 0.52 \times 10^{  20} J\) \(U_{10} = \frac{A}{{r_{10} }} = \frac{{23.04 \times 10^{  29} }}{{69.34 \times 10^{  9} }} \approx 0.33 \times 10^{  20} J\) \(U_{{T_{{}} x_{1} }}^{  } = \sum\nolimits_{i = 1}^{10} {U_{i} } = 18.38 \times 10^{  20} J\)  \(U_{1} = \frac{A}{{r_{1} }} = \frac{{23.04 \times 10^{  29} }}{{42.04 \times 10^{  9} }} \approx 0.55 \times 10^{  20} J\) \(U_{2} = \frac{A}{{r_{2} }} = \frac{{23.04 \times 10^{  29} }}{{20 \times 10^{  9} }} \approx 1.15 \times 10^{  20} J\) \(U_{3} = \frac{A}{{r_{3} }} = \frac{{23.04 \times 10^{  29} }}{{26.91 \times 10^{  9} }} \approx 0.86 \times 10^{  20} J\) \(U_{4} = \frac{A}{{r_{4} }} = \frac{{23.04 \times 10^{  29} }}{{38 \times 10^{  9} }} \approx 0.61 \times 10^{  20} J\) \(U_{5} = \frac{A}{{r_{5} }} = \frac{{23.04 \times 10^{  29} }}{{18.11 \times 10^{  9} }} \approx 1.27 \times 10^{  20} J\) \(U_{6} = \frac{A}{{r_{6} }} = \frac{{23.04 \times 10^{  29} }}{{20 \times 10^{  9} }} \approx 1.15 \times 10^{  20} J\) \(U_{7} = \frac{A}{{r_{7} }} = \frac{{23.04 \times 10^{  29} }}{{58.03 \times 10^{  9} }} \approx 0.40 \times 10^{  20} J\) \(U_{8} = \frac{A}{{r_{8} }} = \frac{{23.04 \times 10^{  29} }}{{44.72 \times 10^{  9} }} \approx 0.52 \times 10^{  20} J\) \(U_{9} = \frac{A}{{r_{9} }} = \frac{{23.04 \times 10^{  29} }}{{22.09 \times 10^{  9} }} \approx 1.04 \times 10^{  20} J\) \(U_{10} = \frac{A}{{r_{10} }} = \frac{{23.04 \times 10^{  29} }}{{44.72 \times 10^{  9} }} \approx 0.52 \times 10^{  20} J\) \(U_{{T_{{y_{1} }} }}^{  } = \sum\nolimits_{i = 1}^{10} {U_{i} } = 8.05 \times 10^{  20} J\) 
Proposed QCA fulladder
This fulladder is designed using the planar designing concept. The proposed FA has been implemented using 2inverters and 2MVs. In comparison with the earlier FA (Azghadi et al. 2007), it has an extra inverter gate. The structure of proposed MV_{5}, it would be easier to employ 2inverters rather than 1inverter and some wires for transmitting the inverted signal to other part. The proposed QCA FA is simple in structure and easy to construct. In this design, at first the carry value is calculated and then takes its inversion value and uses this value as an input of the MV_{5} gates.
Power dissipation of proposed QCA fulladder
The power dissipates from a single cell depends on the rate of change of the clock and the tunneling energy. The power dissipation of a QCA circuit in a single clock phase can be simply calculated by adding the power dissipated by each majority gate and inverter (Liu et al. 2012).
Using Hamming distance (HD) power dissipation of a QCA circuit can be estimated. Power dissipation is depends on HD between input cells to inverter cells as well as HD between majority voter gates (Liu et al. 2012). For an inverter when the input is changed from 0 → 0 or 1 → 1. In this case the HD will be 0, and the power dissipation by inverter at γ = 0.25 E _{ k } and T = 2.0 K is 0.8 meV whereas for γ = 1.0 E _{ k }, it is 8.0 meV (Liu et al. 2012). If the input is changed from 0 → 1 or 1 → 0, in this case the HD will be 1 and the power dissipation by the inverter is 28.4 meV, where T = 2.0 K and γ = 0.25 E _{ k }. For majority gate, power dissipation is minimum, when the inputs are changed from 000 → 000 i.e. HD is 0, and the power dissipation is maximum when polarization of all inputs are changed i.e. input polarization are changed from 000 → 111 i.e. HD is 3. The power dissipation by the majority voter gate for HD 0 and 3 are 0.8 and 41.0 meV respectively, where γ = 0.25 E _{ k } and T = 2.0 K (Liu et al. 2012).
Power dissipation of proposed five input majority gate and QCA full adder
Power dissipation at T = 2.0 K  

γ = 0.25 E _{ k } (meV)  γ = 0.50 E _{ k } (meV)  γ = 0.75 E _{ k } (meV)  γ = 1.0 E _{ k } (meV)  
Five input majority gate  75.3  77.8  80.6  84.5 
QCA fulladder  125.9  129.1  136.8  145.4 
Simulations and results comparison
Comparison of QCA fulladders in terms of gate count, area and latency
Full adder  Type of full adder  Complexity (cells)  Area (μm^{2})  Latency (clock cycle) 

FA [1]  Coplanar QCA FA (Vetteth et al. 2002)  292  0.62  3.5 
FA [2]  Robust QCA FA (Kim et al. 2007)  220  0.36  3 
FA [3]  Coplanar QCA FA (Wang et al. 2003)  145  0.17  1.25 
FA [4]  TypeI QCA FA (Cho and Swartzlander 2007)  135  0.14  1.25 
FA [5]  Multilayer QCA FA (Zhang et al. 2005)  108  0.10  1 
FA [6]  The Robust QCA FA (Hänninen and Takala 2010)  102  0.10  2 
FA [7]  86  0.10  0.75  
FA [8]  Robust QCA FA (Hashemi et al. 2012)  79  0.05  1.25 
FA [9]  Multilayer QCA FA (Navi et al. 2010)  73  0.04  0.75 
FA [10]  Multilayer QCA FA (Qanbari and SabbaghiNadooshan 2013)  63  0.05  0.75 
Proposed full adder  48  0.03  0.75 
Reliability of proposed QCA circuits
Conclusion
A new flexible 5input majority gate and a new efficient fulladder have been presented. The proposed MV_{5} has been implemented in one layer and using nine QCA cells only. To validate the correctness and effectiveness of the proposed MV_{5} a QCA FA has been presented. Moreover the estimation of power dissipation by the proposed QCA fulladder circuits illustrates that the proposed QCA FA is highly energy efficient circuit. The proposed FA has a considerable improvement in comparison to the previous FAs in terms of covered area, number of cells and has a similar time delay to the previous best FA.
Declarations
Authors’ contributions
ANB designed the logic of proposed circuits and simulated them using QCADesigner. SW helped to calculate the power dissipation and temperature effect on AOP of proposed circuits. All authors read and approved the final manuscript.
Acknowledgements
We express our thanks to NH, Nazir Hossain, for his valuable guideline in preparing manuscript.
Competing interests
Both authors declare that they have no competing interests.
Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
Authors’ Affiliations
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