- Technical note
- Open Access
Multi-objective optimization of MOSFETs channel widths and supply voltage in the proposed dual edge-triggered static D flip-flop with minimum average power and delay by using fuzzy non-dominated sorting genetic algorithm-II
- Farshid Keivanian^{1}Email author,
- Nasser Mehrshad^{1} and
- Abolfazl Bijari^{1}
- Received: 2 June 2015
- Accepted: 6 October 2015
- Published: 22 August 2016
Abstract
Background
D Flip-Flop as a digital circuit can be used as a timing element in many sophisticated circuits. Therefore the optimum performance with the lowest power consumption and acceptable delay time will be critical issue in electronics circuits.
Findings
The newly proposed Dual-Edge Triggered Static D Flip-Flop circuit layout is defined as a multi-objective optimization problem. For this, an optimum fuzzy inference system with fuzzy rules is proposed to enhance the performance and convergence of non-dominated sorting Genetic Algorithm-II by adaptive control of the exploration and exploitation parameters. By using proposed Fuzzy NSGA-II algorithm, the more optimum values for MOSFET channel widths and power supply are discovered in search space than ordinary NSGA types. What is more, the design parameters involving NMOS and PMOS channel widths and power supply voltage and the performance parameters including average power consumption and propagation delay time are linked. To do this, the required mathematical backgrounds are presented in this study.
Conclusion
The optimum values for the design parameters of MOSFETs channel widths and power supply are discovered. Based on them the power delay product quantity (PDP) is 6.32 PJ at 125 MHz Clock Frequency, L = 0.18 µm, and T = 27 °C.
Keywords
- Optimum MOSFETs channel widths and power supply
- Proposed Dual Edge-Triggered Static D Flip-Flop
- Minimization of average power and delay
- Power delay product
- Fuzzy NSGA-II
Background
The layout of an electronics circuit plays an important role in the design and usability of many products (Mihajlovic et al. 2007). In computers, communications, and many other systems, the flip-flops are fundamental building blocks. They are the important timing elements in digital circuits which have great impacts over power consumption and speed. The performance of Flip-Flop influence the performance of whole synchronous circuit, particularly in deep pipelined design (Bhargavaram and Pillai 2012). In this study, D Flip-Flop is considered. The optimum layout design of D Flip-Flop can be defined as an optimization problem. That is solved by the Multi-objective Evolutionary Algorithm (MOEA). MOEAs are well-suited for solving several complex multi-objective problems with two or three objectives (Lücken et al. 2014). As the performance of most MOEAs for problems with four or more conflicting objectives is severely deteriorated (Lücken et al. 2014), for this study, we define two conflicting objectives. Here we use a multi-objective evolutionary algorithm based on Genetic Algorithm. The non-dominated sorting genetic algorithm-II, NSGA-II, has questionable exploratory capability (Coello Coello et al. 2007). There are three evolutionary processes such as mutation, crossover, and selection. The mutation operator is used to increase the diversity of off-springs or generated solutions which is inspired by genetic diversity from one generation of population chromosomes to the next. The crossover which is inspired by genetic inheritance in parent children is applied to vary the situation or features of a chromosome or chromosomes from one generation to the next. The selection procedure is done to select the better or more optimum solutions.
In this study, for the proposed problem we will define two objective functions such as average power consumption and propagation delay time. They are minimized by proposed FNSGA-II when its three operators are implemented. For multi-objective optimization we are looking for the series of non-dominated solutions that are placed in the category of Pareto Front. There will not be any other solution better than non-dominated solutions and no solution will dominate them. The solutions of Pareto Front are ranked as the first Front F1 since they are the closest Front to the ideal solution in comparison with the other solutions (Coello Coello et al. 2007).
In sequential circuits there are many Flip-Flops. Since changes in the data inputs of a gated D latch flip-flop have no effect unless the clock is asserted, the propagation delay is not considered when the data inputs are entered (Mohanram 2014). In combinational logic circuits the basic blocks are the gates while in sequential logic circuits the flip flops are principal building blocks. Flip-Flops are clock based devices. Each flip flop can store one bit. D Flip Flop is the best choice in Integrated Circuit design works (Elias 2014). The D flip-flop is also known as a “data” or “delay” flip-flop. It captures the value of the D-input at a definite portion of the clock cycle and then the captured value becomes output Q. The D flip–flip is one of the most common types of flip-flops. Like all Flip Flops, it has the ability to retain one bit of digital information. D flip-flop is applicable for synchronous circuits. In this paper NSGA, NSGA-II, and proposed FNSGA-II are employed to find the best channel widths and supply voltage in which the D Flip-Flop has the lowest average power and propagation delay of proposed dual edge-triggered static D flip-flop circuit. This study is the further research of the previous article which was the single objective optimization of JK Flip-Flop layout sizes based on single objective optimization algorithms such as Ant Colony Optimization in Real or continuous domain ACOR, Fuzzy-ACOR, Genetic Algorithm GA, and Fuzzy-GA in which one objective function, the average power, was considered for minimization (Keivanian et al. 2014a).
Proposed dual-edge triggered D flip-flop
Overall, the operation of the circuit is to select input DATA and pass it on the output channel, Q. As it is illustrated in Fig. 1, the circuit is a synchronous multiplexer that can transmit multiple data simultaneously to output Q based on both edges of CLOCK pulse. In close view, to analyse the performance of circuit, two NMOSs of M17 and M18 were connected to each inverter module (one is M13 and M14, the other is M15 and M16) in order to boost their outputs. Back to back connected inverters keep the data when transmission gate is off. At the same time multiplexer transmits this latched data to the inverter to pass the correct DATA on the output line Q. Based on Fig. 1, when the CLOCK is low the MOSFETs M3, M4 and M18 are all on while M5, M6 and M17 are all off. Hence DATA is hold by negative latch and is passed to output line Q. In contrast, whenever CLOCK is high then the MOSFETs M5, M6 and M17 will be on but the MOSFETs M3, M4 and M18 will be off. In this state, DATA is passed on the output channel Q. So that, in dual edge-triggered D flip-flip DATA is put forward to output through both low and high states of CLOCK. Before the next CLOCK, if DATA alters this new amount of DATA is held by positive edge latch data PELD part and whenever next CLOCK comes and changes from Low to High this DATA is conveyed to the output channel Q. On the contrary, before the following CLOCK, if DATA changes this new DATA is hold by Negative Edge Latch Data NELD part and once next CLOCK arrives and alters from High to Low the DATA reach to the output channel Q. Without using M19, M20, M21, M22, M23, and M24 the output does not reach to the standard value of high or low level and there will be some transient time states for output signals. They should be a series of standard pulses since the input data is in fact a series of standard pulses.
The design and performance parameters of dual edge-triggered D flip-flop in this article
Design parameters | Performance parameters |
---|---|
Supply voltage (V_{DD}) | Total average power (P_{t}) |
PMOS channel width (W_{PMOS}) | |
NMOS channel width (W_{NMOS}) | Propagation delay time (t_{PD}) |
In this article all the channel lengths are set as the fixed value and equal to 0.18 micron L = 0.18 µm, whereas the channel widths are defined as the design parameters in circuit layout design literature and as the decision variables in meta-heuristic based optimization algorithms’ literature.
Single-objective optimization
The minimization of average power Pavg (w) is addressed to single objective optimization problem and many techniques are demonstrated in this literature (Keivanian et al. 2014a, b; Keivanian 2014). For example, for single objective optimization of JK flip flop layout sizes the least dynamic average power obtained was 1.6 nw. But the propagation delay was not considered for optimization as a result the layout sizes could not provide the optimum speed for the circuit. This encouraged us to study more on the multi-objective optimization algorithms and the design and performance parameters of proposed dual edge-triggered static D flip-flop circuit in order to minimize its dynamic average power dissipation and propagation delay.
Multi-objective optimization
Although single-objective optimization problems may have a unique optimal solution, multi-objective optimization problems, MOPs present a possible uncountable set of solutions, which when evaluated, produce vectors whose components represent trade-offs in objective space. Here the objective space is two dimensional including power consumption and delay objectives. In multi-objective optimization area a decision maker finally chooses an acceptable solution or solutions by selecting one or more of the solutions (Coello Coello et al. 2007). In this research work, the decision maker in fact is the electronic designers who evaluate the conditions and choose a candidate solution from the obtained set of solutions that it will have a minimum power delay product value.
The vector of decision variables in the Multi-objective optimization problem is found and satisfies the constraints and optimizes the objective functions (Coello Coello et al. 2007). These functions form a mathematical description of performance of problem which are usually in conflict with each other. In this article there is conflict between propagation delay and dynamic power dissipation (Singh and Sulochana 2013). The design parameters of problem are discovered to find optimum power consumption with reasonable delay time. So both will not be ideally obtained and a trade-off between them is required. Hence, the term “optimizes” means finding such a solution which would give the values of all the objective functions acceptable to the decision maker (Coello Coello et al. 2007).
In this article, our goal is to achieve a candidate solution for layout sizes and power supply values of circuit that will lead to a circuit with 6.32 PJ power delay product. So we firstly try to obtain optimum set of solutions with good performance then select a candidate solution from them with PDP = 6.32 PJ.
Decision variables
Constraints
The channel length L is from the source to drain, and it is a fixed parameter L = 0.18 µm. As the size of MOSFETs continues to scale down, the channel length becomes equal to or less than the depletion layer width of the source and drain junctions, and hence long-channel behavior occurs in short-channel devices(Li 2006).
Objective functions
There will not one unique solution instead a set of solutions will be produced which are based on the Pareto Optimality Theory (Ehrgott 2006).
Dependency between total average power, channel widths, and supply voltage
The relation (12) shows that there is a direct relation between V _{DD} ^{2} and total average power P_{t}.
The relation (15) shows the direct relation between the channel widths and the Total Average Power.
Dependency of propagation delay time t_{PD} to the channel widths W and V_{DD}
The relation (15) shows that the propagation delay time is inversely proportional to the squared supply voltage; therefore increasing the supply voltage is the most effective way to reduce the Propagation Delay Time.
When the supply voltage value is increased, the charging current of the switching capacitances in the circuit is increased this will decrease the propagation delay through the logic, so the maximum frequency of the circuit or the maximum speed of flip-flop is increased (Varnes 2013).
The relation (20) indicates that there is a reverse relation between channel width w and the total propagation delay (t_{PD}).
Implementations in HSPICE software
The command statements of HSPICE (.sp file) are including: 1. Clock (Low level = GND, High level = VDD, pulse width = 4 ns, and period time = 8 ns), 2. Input Data (“1111010110010000” with 7.5 ns time duration for each bit, Low level = GND, and High level = VDD), 3.Selection the MOSFETs model, and 4.Transient Analysis and Measurement of Total Average Power and Propagation Delay Time.
MOSFET model for proposed dual edge-triggered-static D flip-flop
In Simulation Program for Integrated Circuit Engineering, SPICE, the models are defined for MOSFET devices. These models can be divided into three groups: (a) First Generation Level 1, Level 2, and Level 3 Models, (b) Second Generation BISM, HSPICE Level 28, BSIM2 and Third Generation Models, and (c) BSIM3, Level 7, Level 49 … models. The state-of-art models have better performances concerning the short channel effects, local stress, transistors’ operation in the sub-threshold region, gate Leakage tunneling, noise calculations, and temperature variations. In these new models the equations can converge better during circuit simulations (Lynn Fuller 2011). The level 49 model is the enhanced version of BSIM3v3. This compliance includes numerically identical model equations, and range limit parameters.
Through the DC model comparisons it is concluded that Third generation MOSFET models such as Level 7 for OrCAD/PSPICE or Level 49 models for HSPICE give better results than any of the first or second generation models.
The level 49 BSIM3 Version 3 MOS Model is originated from UC Berkeley and it has been installed as Level 49 in HSPICE software (Moon 1998). The performance of level 49 has been improved by reducing the complexity of model equation, replacing some calculations with spline functions, and optimizing the compiler. The simulation results will have time reduction up to 35 % (Star-HSPICE Manual-Release 2001).
In this article, we have used BSIM3v3 LEVEL = 49, VERSION = 3.22 model for NMOS and PMOS MOSFETs.
Link between HSPICE and MATLAB
Implementation of MATLAB
Initial setting of the parameters in NSGA-II
Initial setting of the parameters in NSGA-II
Number of decision variables | 3 |
Maximum iteration | 50 |
Population size | 27 |
Crossover percentage | 0.7 |
P single point | 0.1 |
P double point | 0.2 |
Mutation percentage | 0.4 |
Mutation rate (mu) | 0.02 |
By considering the constraints of (2) and (3), the design parameters are generated within the interval [Var_{min} Var_{max}]. These maximum and minimum values are inspired by physical limitations of circuit. The Sigma value affects the exploration capability of the algorithm and it is named the mutation step. The coefficient is less than one to decrease the computational time and keeps a reasonable exploration capability for algorithm.
M is set one or two or three. One refers to single point crossover, two refers to double point crossover, and three refers to uniform distribution crossover type.
Non-dominated sorting genetic algorithms: NSGA and NSGA-II
In the literature of non-dominated sorting Genetic Algorithm, there is NSGA approach that was relatively successful during several years for example in Coello Coello et al. (2007), and Reed et al. (2001), in this study we also implement and apply it for optimization of our problem.
Performance measurement: r
Proposed fuzzy NSGA-II algorithm: FNSGA-II
The mutation and crossover rates can be changed adaptively during the implementation runs. In this part, a fuzzy inference system FIS is proposed to balance between exploration and exploitation capabilities of NSGA-II algorithm, so the Mutation Percentage and Crossover Percentage are updated in each iteration step. They will determine the exploration and exploitation respectively.
The fuzzy rules in FIS system
Rules | 1 | 2 | 3 | 4 | 5 |
---|---|---|---|---|---|
If | It is low and r is high | It is low and r is low | It is low and r is medium | It is medium and r is medium | It is high and r is low |
Then | Mutation is high, crossover is low | Mutation is low, crossover is high | Mutation is high, crossover is low | Mutation and crossover medium | Mutation is low, crossover is high |
Implementation results
Performance measure r
Algorithm | Performance measure r |
---|---|
NSGA | 2.5 |
NSGA-II | 2.3 |
FNSGA-II | 2 |
The measurement results show that the proposed Fuzzy NSGA-II outperforms the other comparing algorithms therefore we apply it for optimization of layout sizes and power supply in dual edge-triggered static D flip-flop circuit.
Candidate Solutions obtained by algorithms
Algorithm | Design parameters | Performance parameters | Power delay product (PDP) (PJ) |
---|---|---|---|
FNSGA-II | V_{DD} = 1.17 v | Total average power P_{t} = 172 µw | 6.32 |
W_{PMOS} = 1.37 µm | |||
W_{NMOS} = 1.02 µm | Propagation delay t_{d} = 3.676e−08 | ||
NSGA-II | V_{DD} = 1.21 v | Total average power P_{t} = 175 µw | 6.65 |
W_{PMOS} = 1.27 µm | |||
W_{NMOS} = 1.01 µm | Propagation delay t_{d} = 3.8e−08 | ||
NSGA | V_{DD} = 1.30 v | Total average power P_{t} = 180 µw | 7.20 |
W_{PMOS} = 1.15 µm | |||
W_{NMOS} = 1.00 µm | Propagation delay t_{d} = 4e−08 |
Conclusion
A new dual edge-triggered static D Flip-Flop with two NMOS MOSFETs is proposed. The design parameters including NMOS/PMOS channel widths and power supply V_{DD} and performance parameters such as average power consumption and delay are investigated. The required background mathematics showed the relationships between them. So a black box of multi-objective optimization algorithm can be defined because the input and output variables are clarified. We then proposed a fuzzy inference system FIS that contains some fuzzy rules. They are fired during the iteration steps to adaptively tune the exploration and exploitation parameters of proposed Fuzzy Non-dominated Sorting Genetic Algorithm, NSGA-II. The literature showed that the two parameters of GA, P _{ mutation }, and P _{ crossover } may significantly influence the performance of the algorithm. FNSGA-II handles this problem by performing an automatic adaptation of the two parameters of GA taking into account both the global and local optimization, thus diminishing the problem of falling into local minima. The exploration parameters are decreased during the execution of FNSGA-II aiming to quickly find the optimal solution. The iterative link between MATLAB’s algorithm and HSPICE layout design circuit is continued until the stopping criteria, the maximum iteration. Finally FNSGA-II proposed in this paper enables finding solutions that are better distributed the region of solutions of two objective functions. The layout design of suggested Dual Edge-Triggered Static D Flip-Flop Circuit is completed because the optimum values for PMOS and NMOS channel widths W_{PMOS} and W_{NMOS} also the optimum amount for power supply value V_{DD} are obtained by FNSGA-II and base on these values the circuits met the minimum average power and propagation delay time. The power delay product PDP became 6.32 PJ that is good for critical design sensitive to the time and power.
Declarations
Authors’ contributions
FK: Proposing an optimum fuzzy inference system to adaptively harness the control parameters of non-dominate sorting genetic algorithm in fuzzy NSGA-II with fuzzy rules and that is applied for multi-objective optimization of a newly proposed dual edged trigger D Flip-Flop circuit layout design, NM presentation of background mathematics to show the relationship between the design and performance parameters for definition of the circuit layout design as an optimization problem, and AB: In simulation parts and obtaining optimum design parameters for MOSFET channel widths and power supply. All authors read and approved the final manuscript.
Author information
Farshid Keivanian Master of Science in Electronics Engineering 2013–2015, University of Birjand, Iran, GPA: 19.06 Research Interests are Fuzzy Machine Learning, Fuzzy Image Processing, Meta-heurisitc based Optimization in search space, Optimum Fuzzy Rules to control heuristic algorithms’ performance adaptively, Electronics Circuit Layout Optimization. Nasser Mehrshad Associate Professor, University of Birjand, Iran. Research interests: Image Processing, Human Visual Systems, Signal Processing, Biomedical Instrumentations. Abolfazl Bijari Assistant Professor, University of Birjand, Iran. Research interests: Micromechanical frequency-selective devices, RF MEMS switches, Nonlinear effects on MEMS-based devices, Polymer-based MEMS devices, Coplanar Waveguide (CPW) filters.
Competing interests
The authors declare that they have no competing interests.
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Authors’ Affiliations
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