Table 5 Candidate Solutions obtained by algorithms
Algorithm | Design parameters | Performance parameters | Power delay product (PDP) (PJ) |
|---|---|---|---|
FNSGA-II | VDD = 1.17 v | Total average power Pt = 172 µw | 6.32 |
WPMOS = 1.37 µm | |||
WNMOS = 1.02 µm | Propagation delay td = 3.676e−08 | ||
NSGA-II | VDD = 1.21 v | Total average power Pt = 175 µw | 6.65 |
WPMOS = 1.27 µm | |||
WNMOS = 1.01 µm | Propagation delay td = 3.8e−08 | ||
NSGA | VDD = 1.30 v | Total average power Pt = 180 µw | 7.20 |
WPMOS = 1.15 µm | |||
WNMOS = 1.00 µm | Propagation delay td = 4e−08 |