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Table 1 The design and performance parameters of dual edge-triggered D flip-flop in this article

From: Multi-objective optimization of MOSFETs channel widths and supply voltage in the proposed dual edge-triggered static D flip-flop with minimum average power and delay by using fuzzy non-dominated sorting genetic algorithm-II

Design parameters

Performance parameters

Supply voltage (VDD)

Total average power (Pt)

PMOS channel width (WPMOS)

NMOS channel width (WNMOS)

Propagation delay time (tPD)

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