A new approach of presenting reversible logic gate in nanoscale
- Ali Newaz Bahar^{1}Email author,
- Sajjad Waheed^{1} and
- Nazir Hossain^{2}
https://doi.org/10.1186/s40064-015-0928-4
© Bahar et al.; licensee Springer. 2015
Received: 13 November 2014
Accepted: 16 March 2015
Published: 31 March 2015
Abstract
Conventional lithography-based VLSI design technology deployed to optimize low-powered-computing and higher scale integration of semiconductor components. However, this downscaling trend confronts serious challenges of tunneling and leakage current increment to the Complementary Metal–Oxide–Semiconductor (CMOS) technology on nanoscale regimes. To resolve the physical restriction of the CMOS, Quantum-dot Cellular Automata (QCA) technology dedicates for the nanoscale technology that embrace a new information transformation technique. However, QCA is limited to the design of the sequential and combinational circuits only. This paper presents some highly scalable features reversible logic gate for the QCA technology. In addition, proposed layout compared with CMOS technology, offer a better reduction in size up to 233 times.
Keywords
Introduction
Over the years, the reversible logic has attained a great attention due to their ability of power minimization which is the main requirement in the low power VLSI design. This technology is a promising computing paradigm that has immense applications in emerging technologies such as quantum dot cellular automata, quantum computing, optical computing, DNA computing, optical information processing, etc. (Al-Rabadi 2004; Ma et al. 2008; Thapliyal and Ranganathan 2008; Thapliyal and Ranganathan 2009a; Thapliyal and Ranganathan 2010). In reversible circuits the input and output mapping is one-to-one that means every unique output vector is generated from each input vector, and vice versa. It has shown by (Landauer 1961) that the loss of every bit of information dissipates energy of kTln2 joules, where k is Boltzmann’s constant and T is the absolute temperature. In room temperature T _{ R }, the amount of heat generated due to one bit of information loss (Landauer 1961) is small, which is calculated as 2.9 × 10^{−21} joule, but is not negligible. Later on, (Bennett 1973) showed that the energy losses could be avertable; if the computation is carried out by reversible circuits.
Now-a-days, CMOS technology is imminent to its physical boundary in downscaling and confronting critical challenges of designing ultra low power consuming computational devices. This projected the expectation to go looking new technologies that offer emerging solutions. One of the alternatives is known as Quantum-dot Cellular Automata (QCA) (Lent et al. 1993a; Lent et al. 1993b) which has recently been recognized as one of the top emerging technologies with potential applications in future computing (Orlov et al. 1997; Wilson et al. 2002) for its express speed, nanoscale integration and ultra low power consumption in various computational applications (Lent et al. 1993a).
Molecular QCA can operate at room temperature shown in (Lent et al. 2003; Wang and Lieberman 2004). Since the emancipation of QCA, a number of QCA-based logic circuits have been proposed based on majority voter gate, inverter and QCA wires. A lot of QCA based combinational (Azghadi et al. 2007; Cho and Swartzlander 2007; Cho and Swartzlander 2009; Gin et al. 1999; Hänninen and Takala 2010; Ke-ming and Yin-shui 2007; Kim et al. 2007; Mardiris and Karafyllidis 2010; Navi et al. 2010; Sara et al. 2012; Sayedsalehi et al. 2011; Srivastava and Bhanja 2007; Tougaw and Lent 1994; Vetteth et al. 2002; Wang et al. 2003; Zhang et al. 2005), sequential (Askari et al. 2008; Dehkordi et al. 2011; Ghosh et al. 2013; Huang et al. 2007; Sen et al. 2013; Vankamamidi et al. 2008; Venkataramani et al. 2008; Wu et al. 2014; Xiao et al. 2012; Yang et al. 2010) circuits have been proposed in recent years. However, reversible logic circuit designs (Bahar et al. 2013; Shah et al. 2012) in QCA are still unexplored research area. In this paper, four novel QCA circuit layouts of reversible logic gate have been presented and their functionality has been verified using the QCADesigner (Walus et al. 2004).
Material and methods
Where, ρ _{ i } denotes the electronic charge at dot i.
Proposed circuits and presentation
A reversible logic gate is one that has n input n output; with one-to-one mapping that means it determines the outputs from the inputs. It also helps the inputs to be uniquely recovered or reconstructed from the outputs.
NFT gate
TR gate
R gate
BVF gate
Simulations and result analysis
Performance analysis of proposed gates
Parameters | NFT gate | TR gate | R gate | BVF gate |
---|---|---|---|---|
Number of cells | 128 | 68 | 105 | 82 |
Number of majority voter gate | 9 | 6 | 6 | 6 |
Time delay (clock cycle) | 0.5 | 0.75 | 0.75 | 0.5 |
Covered area (size) in QCA (μm^{2}) | 0.142 | 0.079 | 0.126 | 0.10 |
Covered area (size) in CMOS (μm^{2}) | 33.02 | 12.3 | 12.3 | 8.3 |
Improvement (in times) | 233 | 156 | 98 | 83 |
Conclusion
Quantum-dot cellular automata, one of the promising nanotechnologies that are appropriate for the design of highly scalable logic circuits. A number of QCA-based reversible logic gates, which are significantly smaller size than CMOS have been presented here. In addition, QCA design accomplished by the basic gate and logic circuit in which less area is required to make a device. Thus the new device will consume less power and increase device performance. Since nanotechnology has high demand in the market, this QCA technology can be best suited substitute of CMOS based technology.
Declarations
Acknowledgements
We express our thanks to AH, Ahsan Habib, for his valuable guideline in preparing manuscript.
Authors’ Affiliations
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