Table 1 Performance analysis of proposed gates
From: A new approach of presenting reversible logic gate in nanoscale
Parameters | NFT gate | TR gate | R gate | BVF gate |
|---|---|---|---|---|
Number of cells | 128 | 68 | 105 | 82 |
Number of majority voter gate | 9 | 6 | 6 | 6 |
Time delay (clock cycle) | 0.5 | 0.75 | 0.75 | 0.5 |
Covered area (size) in QCA (μm2) | 0.142 | 0.079 | 0.126 | 0.10 |
Covered area (size) in CMOS (μm2) | 33.02 | 12.3 | 12.3 | 8.3 |
Improvement (in times) | 233 | 156 | 98 | 83 |