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Chrestenson transform FPGA embedded factorizations
 Michael J. Corinthios^{1}Email author
 Received: 26 August 2015
 Accepted: 25 August 2016
 Published: 8 September 2016
Abstract
Chrestenson generalized Walsh transform factorizations for parallel processing imbedded implementations on field programmable gate arrays are presented. This general base transform, sometimes referred to as the Discrete Chrestenson transform, has received special attention in recent years. In fact, the Discrete Fourier transform and Walsh–Hadamard transform are but special cases of the Chrestenson generalized Walsh transform. Rotations of a basep hypercube, where p is an arbitrary integer, are shown to produce dynamic contentionfree memory allocation, in processor architecture. The approach is illustrated by factorizations involving the processing of matrices of the transform which are function of four variables. Parallel operations are implemented matrix multiplications. Each matrix, of dimension N × N, where N = p ^{ n }, n integer, has a structure that depends on a variable parameter k that denotes the iteration number in the factorization process. The level of parallelism, in the form of M = p ^{ m } processors can be chosen arbitrarily by varying m between zero to its maximum value of n − 1. The result is an equation describing the generalised parallelism factorization as a function of the four variables n, p, k and m. Applications of the approach are shown in relation to configuring field programmable gate arrays for digital signal processing applications.
Keywords
 Spectral analysis
 Generalised spectral analysis
 Generalised Walsh transform
 Discrete Chrestenson transform
 Discrete Fourier transform
 Parallel processing
 Hypercube transformations
 Generalradix matrix factorization
Background
Applications of the Discrete Fourier, Walsh–Hadamard and Chrestenson generalized Walsh CGW transforms in spectral analysis and digital signal processing (Corinthios 1985, 2009; Bespalov 2010) have received particular attention in recent years thanks to rapid advances of microelectronics in general and field programmable gate arrays FPGAs in particular. The search for higher processing speeds through increasing levels of parallelism motivate the search for optimal transform factorizations.
In this paper a formalism and an algorithm for configuring and sequencing parallel processors implementing factorizations of the (‘Discrete’) Chrestenson generalized Walsh CGW transform are presented. This general base transform has received special attention in recent years. In fact, Discrete Fourier transform and Walsh–Hadamard transform are but special cases of the CGW transform. The architecture of a digital signal processor is defined as optimal if it leads to a minimization of addressing requirements, of shuffle operations and of the number of required memory partitions (Corinthios 1994). The factorizations are developed with a view to implementation as embedded architectures of presently available FPGAs (Harmut et al. 2010; Huda et al. 2014).
The algorithms and corresponding architectures relate to general base matrix factorizations (Corinthios 2009). Rotations of a basep hypercube, where p is an arbitrary integer, produce dynamic memory allocation, in processor architecture. The approach produces factorizations involving the processing of matrices of the transform which are function of four variables. Parallel operations are implemented matrix multiplications. Each matrix, of dimension N × N, where N = p ^{ n }, n integer, has a structure that depends on a variable parameter k. The level of parallelism, in the form of M = p ^{ m } processors can be chosen arbitrarily by varying m between zero to its maximum value of n − 1. The result is an equation describing the generalised parallelism factorization as a function of the four variables n, p, k and m. Applications of the approach are shown in relation to configuring field programmable gate arrays for digital signal processing applications.
Hypercube transformations have been applied to diversified problems of information processing. The present paper describes an approach for FPGA parallel processor configuration using an arbitrary number M of generalbase processing elements, where M = p ^{ m }, p being the general radix (base) of factorization. The input data vector dimension N, or input data matrix dimension N × N, where N = p ^{ n }, the radix, or base, p of factorization of the transformation matrix, the number of processors M, and the span of the matrix, that is, the spacing between data simultaneously accessed are all variable. A unique optimal solution yielding a progressive degree parallel to massively parallel optimal architectures is presented.
Matrix structures
In what follows some definitions relating to the special structure of sparse, permutation and transformation matrices (Corinthios 1994) are employed. In particular matrix span is taken to mean the distance between two successive nonzero elements along a row or a column. A fixed topology processor is one that accesses data in a fixed geometry pattern where data points are equidistant throughout the different iterations, thus requiring no addressing. A shufflefree algorithm is one that necessitates no data shuffling between iterations. A p ^{ k }optimal algorithm is one that requires access of matrix elements which are spaced by a minimum distance of N/p ^{ k } elements. In addition we adopt the following definitions.
General base processing element
In what follows a generalbase processing element PE with a base, or radix, p is a processor that receives simultaneously p input operands and produces simultaneously p output operands. The PE in general applies arithmetic or weighting operations on the input vector to produce the output vector. In matrix multiplication operations for example the PE applies a p × p matrix to the pelement input vector to produce the pelement output vector. The matrix elements may be real or complex.
Due to the diversified general applicability of such a processing element a universal processing element (UPE), which can be constructed in a 3Dtype architecture has been proposed (Corinthios 1985). In the present context a UPE may be seen simply as a general basep processing element PE as defined above, accepting p inputs, weighting them by the appropriate p × p matrix and producing p output operands.
Pilot elements, pilots matrix
Similarly to signals and images an N × N matrix may be sampled and the result is “impulses”, that is, isolated elements in the resulting N × N samples matrix. We shall assume uniform sampling of rows and columns yielding p uniformly spaced samples from each of p rows and element alignment along columns, that is, p uniformly spaced samples along columns as well as rows. The samples matrix which we may refer to as a “frame” thus contains p rows of p equally spaced elements each, a rectangular grid of p ^{2} impulses, which we may refer to as “poles”, which we shall call a “dispatch”. With N = p ^{ n } the N ^{2} elements of the “main” (or “parent”) matrix, that is, the original matrix before sampling, may be thus decomposed into N ^{2}/p ^{2} = p ^{ n−2} such dispatches.
By fixing the row sampling period as well as the column sampling period, the row and column spans of the resulting matrix are known. It therefore suffices to know the coordinates (indices) of the top left element, that is, the element with the smallest of indices, of a dispatch to directly deduce the positions of all its other poles. The top left element acts thus as a reference point, and we shall call it the “pilot element”. The other p ^{2} − 1 elements associated with it may be called its “satellites”.
A processing element assigned to a pilot element can thus access all p ^{2} operands of the dispatch, having deduced their positions knowing the given row and column spans.
Since each pilot element of a frame originated from the same position in the parent matrix we can construct a “pilots matrix” by keeping only the pilot elements and forcing to zero all other elements of the parent matrix. The problem then is one of assignment, simultaneous and/or sequential, of the M = p ^{ m } processors to the different elements of the pilots matrix.
Hypercube dimension reduction
The extraction of a pilots matrix from its parent matrix leads to a dimension reduction of the hypercube representing its elements. The dimension reduction is in the form of a suppression, that is, a forcing to zero, of one of the hypercube digits. Let C = (j _{ n−1}, …, j _{1} j _{0}), j _{ k } ∊ {0, 1, 2, …, p − 1} be an ndigit basep hypercube. We will write \( C_{{\bar{k}}} \) to designate the hypercube C with the digit k suppressed, that is, forced to zero. Several digits can be similarly suppressed. For example, \( C_{{\overline{2} ,\overline{4} }} = \left( {j_{n  1} \ldots j_{5} 0j_{3} 0j_{1} j_{0} } \right) \), and \( C_{{\overline{n  1} }} = \left( {0j_{n  2} \ldots j_{1} j_{0} } \right) \).
Parallel configuration algorithm
The parallel dispatch, state assignment and sequencing Algorithm 1 dispatches the M = p ^{ m } processors for each stage of the matrix factorization. The basep mtuple (i _{ m−1} i _{ m−2}…i _{1} i _{0}) is assigned to the parallel processors. The (n − m) tuple (j _{ n−1} j _{ n−2}…j _{ m }) is assigned to the sequencing cycles of each processor. The algorithm subsequently applies hypercube transformations as dictated by the type of matrix, the stage of matrix factorization and the number of dispatched processors. It tests optimality to determine the type of scan of matrix elements to be applied and evaluates parameters such as pitch and memory optimal queue length, to be defined subsequently, it accesses the pilot elements and their satellites, proceeding to the parallel dispatch and sequencing of the processing elements.
Each processing element at each step of the algorithm thus accesses from memory its p input operands and writes into memory those of its output operands. The algorithm, while providing an arbitrary, generalised, level of parallelism up to the ultimate massive parallelism, produces optimal multiprocessing machine architecture minimizing addressing, the number of memory partitions as well as the number of required shuffles. Meanwhile it produces virtually wiredin pipelined architecture and properly ordered output.
General matrix decomposition
More generally we may wish to decompose A in an order different from the uniform row and column scanning as in this last equation. In other words we may wish to pick the dispatches at an arbitrary order rather than in sequence. As mentioned above, we shall call the top left element the pilot element and its p ^{2} − 1 companions its satellites. In this last equation the pilot elements are those where k = 1 = 0.
At each clock value K a set of M UPE’s (PE’s) is assigned a set of M dispatches simultaneously. We will reserve the symbols w and z to designate the row and column indices of a pilot element at clock K. In other words, at clock K each selected pilot element shall be designated a _{ w,z }, that is, [A]_{ w,z } where w and z are functions of K to be defined. They will be determined in a way that optimizes the parallel and sequential operations for the given matrix structure and the number M = p ^{ m } of available UPE’s.
Application to the CGW transforms
In the following, for simplicity, the scaling factor \( 1/\sqrt p \) will be dropped. We start by deriving three basic forms of the Chrestenson (generalised Walsh GW) transform in its three different orderings: in natural order CGWN, in Walsh–Paley order CGWP and in Walsh–Kaczmarz order CGWK.
The CGWN transformation matrix
CGWP transformation matrix
CGWK transformation matrix
The following factorizations lead to shufflefree optimal parallelpipelined processors.
CGWN optimal factorization
CGWP optimal factorization
CGWK optimal factorization
The matrices Γ_{ i } are p ^{2}optimal, except for Γ_{0} which is maximal span. These are therefore optimal algorithms which can be implemented by an optimal parallel processor, recirculant or pipelined, with no shuffling cycle called for during any of the n iterations.
Application to image processing
These fast algorithms are all p ^{2}optimal requiring no shuffling between iterations of a pipelined processor. In applying these factorizations the successive iterations are effected on successive subimages such that after log_{ p } N stages the transform image Y is pipelined at the processor output. Applications include realtime processing of video signals.
Perfect shuffle hypercube transformations
The hypercube transformations approach is illustrated using the important matrices of the Chrestenson generalised Walsh–Paley (CGWP), generalised Walsh–Kaczmarz (CGWK) and the Discrete Fourier transforms.
We note that with respect to x the left k digits and the right m digits are left unchanged while the remaining digits are rotated using a circular shift of one digit to the right.
The pilotelements matrix β _{ k } corresponding to the matrix B _{ k } is obtained by restricting the values of w (and hence the corresponding z values) to w = 0, 1, …, p ^{ n−1} − 1.
The CGWP factorization
In evaluating the pilot elements coordinates we begin by setting the number of processors M = 1. The corresponding w − z relation of the pilot elements are thus evaluated with m = 0. Once this relation has been established it is subsequently used as the reference “w − z conversion template” to produce the pilot element positions for a general number of M = p ^{ m } processors. A “right” scan is applied to the matrix in order to produce the w − z template with an ascending order of w. In this scanning type the algorithm advances the first index w from zero selecting pilot elements by evaluating their displacement to the right as the second index z. Once the template has been evaluated the value m corresponding to the number of processors to be dispatched is used to perform successive pary divisions in proportion to m to assign the M processors with maximum spacing, leading to maximum possible lengths of memory queues. A “down” scan is subsequently applied, where pary divisions are applied successively while proceeding downward along the matrix columns, followed by a selection of the desired optimal scan.
 1.k < n − 2
 (a)x: m = 0$$ w \simeq K_{{\overline{n  1} }} $$(67)$$ z \simeq \left[ {\left( {I_{{p^{k} }} \times P_{{p^{n  k} }} } \right)K} \right]_{{\overline{n  2} }} $$(68)
 (b)y: 1 ≤ m ≤ n – k −2$$ w \simeq \left[ {\left( {P_{{p^{k + 1} }} \times I_{{p^{n  k  1} }} } \right)\,\prod\limits_{t = 1}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \times I_{p} } \right)K} } \right]_{{\overline{n  1} }} $$(69)$$ z \simeq \left[ {P_{{p^{n} }} \,\prod\limits_{t = 1}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \, \times \,I_{p} } \right)K} } \right]_{{\overline{n  2} }} $$(70)
 (c)\( z{:}\,n  k  1 \le m \le n  1 \)$$ w \simeq \left[ {\left( {P_{{p^{k + 1} }} \times I_{{p^{n  k  1} }} } \right)\,\prod\limits_{t = 1}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \times I_{p} } \right)K} } \right]_{{\overline{n  1} }} $$(71)$$ z \simeq \left[ {P_{{p^{n} }} \,\prod\limits_{t = 1}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \times I_{p} } \right)K} } \right]_{{\overline{n  2} }} $$(72)
 (a)
 2.\( k = n  2 \)
 (a)\( u{:}\,m = 0 \)$$ \begin{aligned} w & \simeq K_{{\overline{n  1} }} \\ z & \simeq \left[ {\left( {I_{{p^{n  2} }} \times P_{{p^{2} }} } \right)K} \right]_{{\overline{n  2} }} \\ \end{aligned} $$(73)
 (b)\( v{:}\,m \ge 1 \)$$ w \simeq \left[ {\,\prod\limits_{t = 0}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \times I_{p} } \right)K} } \right]_{{\overline{n  1} }} $$(74)\( t{:}\,k = n  1 \)$$ z \simeq \left[ {P_{{p^{n} }} \,\prod\limits_{t = 1}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \times I_{p} } \right)K} } \right]_{{\overline{n  2} }} $$(75)$$ w = z\, \simeq \,\left[ {\,\prod\limits_{t = 0}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \times I_{p} } \right)K} } \right]_{{\overline{n  1} }} $$(76)
 (a)

\( x{:}\,\left( {k < n  2\,,\quad m = 0} \right) \)$$ w = \sum\limits_{j = 0}^{n  2} {p^{t} \,j_{t} } $$(77)$$ z = \sum\limits_{j = 0}^{k  1} {p^{t} \,j_{t} + p^{n  1} \,j_{k} } + \sum\limits_{t = k + 1}^{n  2} {p^{t  1} \,j_{t} } $$(78)

\( y{:}\,k < n  2\,,\quad 1 \le m \le n  k  2 \)$$ w = p^{k} \,i_{0} + \sum\limits_{s = 1}^{m  1} {p^{n  1  s} \,i_{s} \, + \,\sum\limits_{t = m}^{m + k  1} {p^{t  m} \,j_{t} } } \, + \sum\limits_{t = m + k}^{n  2} {p^{t  m + 1} \,j_{t} } $$(79)$$ z = p^{n  1} \,i_{0} + \sum\limits_{s = 1}^{m  1} {p^{n  2  s} } \,i_{s} + \sum\limits_{t = m}^{n  2} {p^{t  m} \,j_{t} } $$(80)

\( z{:}\,k < n  2\,,\quad n  k  1 \le m \le n  1 \)$$ w = p^{k} \,i_{0} + \sum\limits_{s = 1}^{n  k  2} {p^{n  1  s} } \,i_{s} + \sum\limits_{s = n  k  1}^{m  1} {p^{n  2  s} } \,i_{s} + \sum\limits_{s = m}^{n  2} {p^{t  m} } \,j_{t} $$(81)$$ z = p^{n  1} \,i_{0} + \sum\limits_{s = 1}^{m  1} {p^{n  2  s} } \,i_{s} + \sum\limits_{t = m}^{n  2} {p^{t  m} } \,j_{t} $$(82)

\( u{:}\,k = n  2\,,\quad m = 0 \)$$ w = \sum\limits_{t = 0}^{n  2} {p^{t} j_{t} } $$(83)$$ z = \sum\limits_{j = 0}^{n  3} {p^{t} j_{t} } + p^{n  1} \,j_{n  2} $$(84)

\( v{:}\,k = n  2\,,\quad m \ge 1 \)$$ w = \sum\limits_{s = 0}^{m  1} {p^{k  s} \,i_{s} } + \sum\limits_{t = m}^{n  2} {p^{t  m} \,j_{t} } $$(85)$$ z = p^{n  1} \,i_{0} + \sum\limits_{s = 1}^{m  1} {p^{k  s} \,i_{s} } + \sum\limits_{t = m}^{n  2} {p^{t  m} \,j_{t} } $$(86)

\( t{:}\,k = n  1 \)$$ w = z = \sum\limits_{s = 0}^{m  1} {p^{n  2  s} \,i_{s} } + \sum\limits_{t = m}^{n  2} {p^{t  m} \,j_{t} }. $$(87)
Row and column scans for optimal assignment
A processor is considered optimal if it requires a minimum of memory partitions, is shuffle free, meaning the absence of clock times used uniquely for shuffling, and produces an ordered output given an ordered input. It is shown in Corinthios (1994) that p ^{2}optimal algorithms and processors lead to a minimum number of p ^{2} partitions of N/p ^{2} queue length each. With M = p ^{ m } basep processors operating in parallel the number of partitions increases to p ^{ m+2} and the queue length of each partition reduces to N/p ^{ m+2}.
An optimal multiprocessing algorithm should satisfy such optimality constraints. The horizontal spacing between simultaneously accessed pilot elements defines the input memory queue length. The vertical spacing defines the output memory queue length. With M processors applied in parallel the horizontal spacing between the accessed elements will be referred to as the “input pitch”, while the vertical spacing as the “output pitch”.
By choosing the pilot elements leading to the maximum possible pitch, which is the highest of the two values: the minimum input pitch and minimum output pitch, optimality in the form of N/p ^{ m+2} queue length is achieved.
These are the only two cases of the matrix that need be thus modified for optimality. All results obtained above for the other validity conditions can be verified to be optimal.
Matrix span
Each processing element thus accesses p operands spaced p ^{ n−2} points apart and writes their p outputs at points which are p ^{ n−1} points apart.
The CGWK factorization
The \( \Gamma _{k} \) transformations
 1.
\( k = 0 \)
\( a{:}\,k = 0,m = 0 \)

$$ \begin{aligned} w\, &\simeq \,K_{{\overline{n  1} }} \hfill \\ z\, &\simeq P_{{p^{n} }} \,K_{{\overline{n  1} }} \equiv \left[ {\left( {P_{{p^{n  1} }} \, \times I_{p} } \right)K} \right]_{{\overline{n  1} }} \hfill \\ \end{aligned} $$(103)

\( b{:}\,k = 0,m \ge 2 \)$$ w \simeq \,\left[ {\prod\limits_{t = 1}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \, \times \,I_{p} } \right)} \,K} \right]_{{\overline{n  1} }} $$(104)$$ z\, \simeq \,\left[ {\prod\limits_{t = 0}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \times I_{p} } \right)} \,K} \right]_{{\overline{n  1} }} $$(105)

 2.\( 1 \le k \le n  3 \)

\( c{:}\,m = 0 \)$$ w\, \simeq \,\left[ {\left( {I_{{p^{n  2} }} \times P_{{p^{2} }} } \right)K} \right]_{{\overline{n  2} }} $$(106)$$ z\, \simeq \,\left[ {\left( {I_{{p^{k} }} \times P_{{p^{n  k  1} }} \times I_{p} } \right)\,\left( {P_{{p^{n  1} }}^{  1} \times I_{p} } \right)K} \right]_{{\overline{n  1} }} $$(107)

\( d{:}\,m = 1 \)$$ w\, \simeq \,\left[ {\left( {I_{{p^{n  2} }} \times P_{{p^{2} }} } \right)\,\left( {P_{{p^{k} }} \times I_{{p^{n  k} }} } \right)K} \right]_{{\overline{n  2} }} $$(108)$$ z\, \simeq \,\left[ {\left( {I_{p} \times P_{{p^{n  2} }} \times I_{p} } \right)\,\left( {P_{{p^{n  1} }}^{  1} \times I_{p} } \right)K} \right]_{{\overline{n  1} }} $$(109)

\( e{:}\,m \ge 2 \)$$ z\, \simeq \,\left[ {\left( {P_{{p^{n  1} }} \times I_{p} } \right)\,\prod\limits_{t = 2}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \times I_{p} } \right)} \,K} \right]_{{\overline{n  1} }} $$(110)
 (a)\( m \ge n  k \)$$ w \simeq \left[ {\left( {P_{{p^{k} }} \times I_{{p^{n  k} }} } \right)\prod\limits_{t = 1}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \times I_{p} } \right)K} } \right]_{{\overline{n  2} }} $$(111)
 (b)\( 2 \le m \le n  k \)$$ w\, \simeq \,\left[ {\left( {P_{{p^{k} }} \times I_{{p^{n  k} }} } \right)\prod\limits_{t = 1}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \times I_{p} } \right)} \,K} \right]_{{\overline{n  2} }} $$(112)

 3.\( k \ge n  2 \)$$ w\, \simeq \,\left[ {\left( {I_{{p^{n  2} }} \times P_{{p^{2} }} } \right)K} \right]_{{\overline{n  2} }} $$(113)\( g{:}\,m = 1 \)$$ z\, \simeq \,\left[ {\left( {P_{{p^{n  1} }}^{  1} \times I_{p} } \right)\,K} \right]_{{\overline{n  1} }} $$(114)$$ w\, \simeq \left[ {\left( {I_{{p^{2} }} \times P_{{p^{n  2} }} } \right)\,\left( {P_{{p^{n  2} }} \times I_{{p^{2} }} } \right)K} \right]_{{\overline{n  2} }} $$(115)\( h{:}\,m \ge 2 \)$$ z\, \simeq \,\left[ {\left( {P_{{p^{n  2} }}^{  1} \times I_{{p^{2} }} } \right)\,\left( {P_{{p^{n  1} }} \times I_{p} } \right)K} \right]_{{\overline{n  1} }} $$(116)\( i{:}\,2 \le m \le n  2 \)$$ w\, \simeq \,\left[ {\left( {P_{{p^{n  2} }} \times I_{{p^{2} }} } \right)\prod\limits_{t = 1}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \times I_{p} } \right)} \,K} \right]_{{\overline{n  2} }} $$(117)\( j{:}\,m = n  1 \)$$ z \simeq \,\left[ {\left( {P_{{p^{n  1} }} \times I_{p} } \right)\prod\limits_{t = 2}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \times I_{p} } \right)} \,K} \right]_{{\overline{n  1} }} $$(118)$$ z\, \simeq \,\left[ {\left( {P_{{p^{n  1} }} \times I_{p} } \right)\prod\limits_{t = 2}^{m  1} {\left( {I_{{p^{t} }} \times P_{{p^{n  t  1} }} \times I_{p} } \right)} \,K} \right]_{{\overline{n  1} }} $$(119)
CGWK optimal assignments
 1.
\( k = 0 \)
\( a{:}\,k = 0\,,\quad m = 1 \)

$$ \begin{aligned} & w{:}\,0\quad \quad i_{0} \quad \quad j_{n  2} \quad \quad \ldots \quad \quad j_{2} \quad \quad j_{1} \\ & z{:}\,0\quad \quad j_{1} \quad \quad i_{0} \quad \quad j_{n  2} \quad \quad \ldots \quad \quad j_{3} \quad \quad j_{2} \\ \end{aligned} $$

\( b{:}\,k = 0\,,\quad m \ge 2 \)$$ \begin{aligned} & w{:}\,0\quad \quad i_{0} \quad \quad i_{1} \quad \quad \ldots \quad \quad i_{m  1} \quad \quad j_{n  2} \quad \quad \ldots \quad \quad j_{m + 1} \quad \quad j_{m} \\ & z{:}\,0\quad \quad j_{m} \quad \quad i_{0} \quad \quad i_{1} \quad \quad \ldots \quad \quad i_{m  2} \quad \quad j_{n  2} \quad \quad \ldots \quad \quad j_{m + 1} \\ \end{aligned} $$

The CGWK matrix spans
FPGA configuration
Configuring FPGAs to execute digital signal processing algorithms in real time has been rendered readily accessible through model simulation using Matalb^{©} and Simulink. In what follows we summarize results obtained in configuring Xilinx FPGA boards and particular the Artix7 Nexys 4 DDR platform. In these applications the basic Discrete Chrestenson transform matrices with M = 1, p = 2 and n = 5 defining 32point transforms both as the Discrete Fourier transforms and Walsh–Hadamard transforms are presented. In both cases the transform of ramp is evaluated.
Conclusion
A formalism and an algorithm for the parallel implementation of the Chrestenson transform employing rotations of a generalbase hypercube and their embedding into FPGA architectures has been presented. Closedform generalradix factorizations of the transformation matrices, showing processor architecture and sequencing of an arbitrary number M = p ^{ n−1} of generalbase processors have been obtained. Pilot elements addresses and matrix spans to locate their satellites are automatically generated for dispatching and sequencing the parallel processors.
Declarations
Acknowledgements
The information technology support of Saad Chidami in the process of transferring simulation models to FPGA platform is greatly appreciated. The author wishes to acknowledge the research grant received from the National Science and Engineering Council of Canada NSERC.
Competing interests
The author declare that he has no competing interests.
Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
Authors’ Affiliations
References
 Bespalov MS (2010) Discrete Chrestenson transform. Prob Inf Transm 46(4):353–375View ArticleGoogle Scholar
 Corinthios MJ (1985) 3D cellular arrays for parallel/cascade image/signal processing. In: Karpovsky M (ed) Spectral techniques and fault detection. Academic Press, New YorkGoogle Scholar
 Corinthios M (1994) Optimal parallel and pipelined processing through a new class of matrices with application to generalized spectral analysis. IEEE Trans Comput 43(4):443–459View ArticleGoogle Scholar
 Corinthios MJ (2009) Signals, systems, transforms and digital signal processing with Matlab^{©}. Taylor and Francis/CRC Press, LondonGoogle Scholar
 Harmut F, Sadrozinski W, Wu J (2010) Applications of field programmable gate arrays in scientific research. Taylor and Francis, LondonGoogle Scholar
 Huda S, Anderson JH, Tamura H (2014) Optimizing effective interconnect capacitance for FPGA power reduction. In: 22nd ACM/SIGDA international symposium on field programmable gate arrays, Monterey, CA, 26–28 Feb 2014Google Scholar