Design and implementation of an efficient single layer five input majority voter gate in quantum-dot cellular automata

The fundamental logical element of a quantum-dot cellular automata (QCA) circuit is majority voter gate (MV). The efficiency of a QCA circuit is depends on the efficiency of the MV. This paper presents an efficient single layer five-input majority voter gate (MV5). The structure of proposed MV5 is very simple and easy to implement in any logical circuit. This proposed MV5 reduce number of cells and use conventional QCA cells. However, using MV5 a multilayer 1-bit full-adder (FA) is designed. The functional accuracy of the proposed MV5 and FA are confirmed by QCADesigner a well-known QCA layout design and verification tools. Furthermore, the power dissipation of proposed circuits are estimated, which shows that those circuits dissipate extremely small amount of energy and suitable for reversible computing. The simulation outcomes demonstrate the superiority of the proposed circuit.

on majority verdict (Oya et al. 2003). Up to now, most QCA circuits have been investigated and designed only by means of 3-input majority gates (MV 3 ). However, if these circuits are constructed using 5-input majority gates (MV 5 ), they would be optimized in cell counts, area and complexity.
To reveal the effectiveness of proposed MV 5 , a QCA full-adder has been designed using proposed MV 5 . Results reveal the superiority of proposed FA in terms of latency, cell counts and area to other previous designs (Tougaw and Lent 1994;Wang et al. 2003;Zhang et al. 2004;Azghadi et al. 2007;Cho andSwartzlander 2007, 2009).

Proposed five-input majority gate
MV 5 is a cell arrangement which includes five input cells, one output and some device cells. The logic function of MV 5 can be presented as Eq. (1), where the inputs are labeled as A, B, C, D and E respectively. The truth table of the MV 5 is shown in Table 1.
The proposed design of MV 5 is shown in Fig. 1. In this design, A, B, C, D and E are labeled as inputs and the output cell is labeled as OUTPUT. Additionally, three middle cells are labeled 1, 2 and 3. Polarization of input cells are fixed and middle cells and output cell are free to change. Here, cell "A" has an impact on all the middle cells. Similarly, cell "B", cell "C" cell "D" and cell "E" also have an impact on all the middle cells. These impacts are propagated to the output cell and construct the MV 5 output, efficiently. The propose MV 5 requires only nine cells and uses conventional QCA cells to implement.

Physical proofs
To carry out the physical proofs, the below postulates are considered: • All cells are alike and the distance of end to end of each cell is 18 nm.
• The space between two neighbor cells is 2 nm shown in Fig. 2.
The proposed MV 5 has approximately 32 distinct input states; we should verify all the input condition to validate the accuracy of the gate. In this paper, only one state (A = 1, B = 0, C = D = E = 1) has been considered for verification. Similarly, other states can be verified too. For a fixed input MV 5 , the five input cells polarization are remain unchanged; only the intermediary cells and the output cell are subject to be changed to their polarization according to the input cells. Here, the proposed MV 5 have three intermediary cells and one output cell those are labeled as 1, 2, 3 and OUTPUT respectively shown in Fig. 1.
A structure is said to be stable, when the QCA cells are assembled with their minimum potential energies. The potential energy between two different cell electrons can be computed using the Eq. (2) (Halliday and Resnick 2004;McDermott 1984;Halloun and Hestenes 1985). Here, U is potential energy; a fixed colon is k, q 1 and q 2 are electric charges, and the distance between two electric charges is r. The total potential energy of a given structure is "U T " and that can be calculated using Eq. (3).
For, finding the stable structure, one needs to calculate the potential energy U i for each middle cell. Here, cell 1 has two different polarization state; polarization P = +1 and P = −1 shown in Fig. 3. Now, considering state 3 (a); here the potential energy for cell 1 U T is the summation of potential energies of both x and y electrons. Potential energy for x and y electrons are the total energy exist between each electron (e 1 , e 2 , e 3 , e 4 , e 5 , e 6 , e 7 , e 8 , e 9 , and e 10 ) with electron x and y respectively, which is calculated using Eq. (2). Finally, using Eq. (3) total potential energy for "cell 1" can be calculated. Similarly, potential energy of "cell 1" for state 3.3 (b) can be calculated. The necessary calculations for finding the total potential energies of structure (a) and structure (b) are given below: Total potential energy of Fig. 3a is Similarly, the total potential energy for Fig. 3b can be calculated and it is With comparison of the achieved results, the electrons in cell 1 are located in state (a) is more stable because it has the lower potential energy than state (b). Similar the potential energy for cell 2 and cell 3 can be calculated and the final results are mentioned as. Proposed QCA full-adder The proposed MV 5 is implemented by designing an efficient QCA full-adder. The schematic diagram of newly proposed QCA full-adder is shown in Fig. 4. This full-adder is designed using the planar designing concept. The proposed FA has been implemented using 2-inverters and 2-MVs. In comparison with the earlier FA (Azghadi et al. 2007), it has an extra inverter gate. The structure of proposed MV 5 , it would be easier to employ 2-inverters rather than 1-inverter and some wires for transmitting the inverted signal to other part. The proposed QCA FA is simple in structure and easy to construct. In this design, at first the carry value is calculated and then takes its inversion value and uses this value as an input of the MV 5 gates.

Power dissipation of proposed QCA full-adder
The power dissipates from a single cell depends on the rate of change of the clock and the tunneling energy. The power dissipation of a QCA circuit in a single clock phase can be simply calculated by adding the power dissipated by each majority gate and inverter (Liu et al. 2012).
Using Hamming distance (HD) power dissipation of a QCA circuit can be estimated. Power dissipation is depends on HD between input cells to inverter cells as well as HD between majority voter gates (Liu et al. 2012). For an inverter when the input is changed from 0 → 0 or 1 → 1. In this case the HD will be 0, and the power dissipation by inverter at γ = 0.25 E k and T = 2.0 K is 0.8 meV whereas for γ = 1.0 E k , it is 8.0 meV (Liu et al. 2012). If the input is changed from 0 → 1 or 1 → 0, in this case the HD will be 1 and the power dissipation by the inverter is 28.4 meV, where T = 2.0 K and γ = 0.25 E k . For majority gate, power dissipation is minimum, when the inputs are changed from 000 → 000 i.e. HD is 0, and the power dissipation is maximum when polarization of all inputs are changed i.e. input polarization are changed from 000 → 111 i.e. HD is 3. The power dissipation by the majority voter gate for HD 0 and 3 are 0.8 and 41.0 meV respectively, where γ = 0.25 E k and T = 2.0 K (Liu et al. 2012).
By using Hamming distance based methodology described in (Liu et al. 2012), the power dissipated by the proposed MV 5 and 1-bit QCA full-adder is estimated and the results are shown in Table 2.

Simulations and results comparison
The proposed MV 5 and FA have been simulated and verified using QCADesigner  only tools for QCA layout design and verification. In these simulations, both bi-stable and coherence vector engines have been employed to simulate. In both simulations identical outputs are obtained which confirm the correctness of the The proposed QCA full-adder is designed in three layers illustrated in Fig. 6. The main layer contains 34 cells, second layer contains 4 cells and the third layer contains 10 cells. Finally, it requires 48 cells and 3 clock phases to produce exact outputs (Sum and Carry).
Using QCADesigner, complexity, time delay and area consumption of QCA circuits can easily be calculated . Table 3 demonstrates a concise comparison between the proposed QCA FA and the earlier FA (Vetteth et al. 2002;Wang et al. 2003;Zhang et al. 2005;Cho and Swartzlander 2007;Kim et al. 2007;Cho andSwartzlander 2007, 2009;Navi et al. 2010;Hänninen and Takala 2010;Hashemi et al. 2012;Qanbari and Sabbaghi-Nadooshan 2013) in terms of complexity, area and time delay. Here, complexity indicates the number of cell is used to design the FA. Similarly, the area represents the total covered area of the corresponding FA in micro meter. The "Latency" indicates the number of clock zone used. It also indicates the time delay of the circuit.
It is clear that the new QCA full-adder dominates all the previous designs (Vetteth et al. 2002;Wang et al. 2003;Zhang et al. 2005;Cho and Swartzlander 2007;Kim et al. 2007;Cho andSwartzlander 2007, 2009;Navi et al. 2010;Hänninen and Takala 2010;Hashemi et al. 2012;Qanbari and Sabbaghi-Nadooshan 2013) in terms of covered area and number of cell count. It leads to a very dense structure and has the same time delay with the previous best designs (Qanbari and Sabbaghi-Nadooshan 2013). According to the bar chat shown in Fig. 7, the proposed FA leads to around 95.17 % improvement in  area and 83.6 percent improvement in cell complexity in comparison to the QCA FA designed using 3-input majority gates and inverters in (Vetteth et al. 2002). This FA also, leads to around 40 % improvement in area and 23.8 % improvement in cell complexity compared to the best QCA FA designed using previous MV 5 and inverters (Qanbari and Sabbaghi-Nadooshan 2013).

Reliability of proposed QCA circuits
The temperature effect on the output cell's polarization of proposed MV 5 and QCA FA are observed. The output cell's polarization is taken at different temperature using QCADesigner tool. The average output polarization (AOP) for each output cell is calculated from (Pudi and Sridharan 2011) and shown in Fig. 8. The proposed circuit works efficiently in temperature range of 1-6 K, and the AOP for each output cell is changed very little in this range. When the temperature is above 6 K, the AOP is dropped drastically, which results incorrect outputs.

Conclusion
A new flexible 5-input majority gate and a new efficient full-adder have been presented. The proposed MV 5 has been implemented in one layer and using nine QCA cells only. To validate the correctness and effectiveness of the proposed MV 5 a QCA FA has been presented. Moreover the estimation of power dissipation by the proposed QCA full-adder