Table 3 Comparison of main design specifications for CSI, SCI and inverter chain delay elements
From: A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
S. no. | Delay resolution | Delay range | Power consumption | Area | Linearity | Robustness against process variation | Robustness against temperature variation |
|---|---|---|---|---|---|---|---|
1 | SCI | Inv. Chain | CSI | CSI | Inv. chain | Inv. chain | SCI |
2 | CSI | SCI | SCI | SCI | SCI | SCI | CSI |
3 | Inv. chain | CSI | Inv. chain | Inv. chain | CSI | CSI | Inv. chain |