Table 2 Power consumption and area for different delay line types
From: A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
Delay element | Technology (μm) | Delay resolution (ps) | Delay range (ps) | Power consumption | Area | |DNL| (normalized) | |INL| (normalized) | Jitter (RMS) | Control mechanism |
|---|---|---|---|---|---|---|---|---|---|
1. CMOS inverter based on RC differentiator (El Mourabit et al. 2012) | 0.35 | 0.5 | 200 | 100 μW @ 0.5 GHz | 400 μm2 | 0.4 | 0.1 | N/A | Digital |
2. SCI (Pao-Lung et al. 2005) | 0.35 | 1.43 | 40 | 490 μW @ 400 MHz | 850 μm2 | 0.37 | 0.19 | N/A | Digital |
3. CSI (Maymandi-Nejad and Sachdev 2003) | 0.35 (El Mourabit et al. 2012) | 40 | 400 | 211 μW @ 400 MHz | 450 μm2 | – | – | N/A | Digital |
4. Cascaded inverters (Ching-Che and Chen-Yi 2003) | 0.35 | 5 | 300 | 950 μW @ 400 MHz | 0.36 mm2 | – | – | N/A | Digital |