From: A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
Delay element | Technology (μm) | Delay resolution (ps) | Delay range | Power consumption | Area | |DNL| (normalized) | |INL| (normalized) | Jitter (RMS) | Control mechanism |
---|---|---|---|---|---|---|---|---|---|
1. Variable-resistor array (Saint-Laurent and Swaminathan 2001) | 0.18 | 1 | 50Â ps | N/A | N/A | 1.37 | 1.04 | N/A | Digital |
2. Inverter matrix (Abas et al. 2007a) | 0.18 | 2 | 116 ps | N/A | 3465 μm2 | 2.7 | 3.11 | N/A | Digital |
3. SCI (Abas et al. 2007a) | 0.18 | 2 | 32 ps | N/A | 1140 μm2 | 0.25 | 1 | N/A | Digital |
4. Supply modulation-based (Moazedi et al. 2011) | 0.18 | 30 | 1.34Â ns | 0.4Â mW | N/A | 9 | 17 | 9.5Â ps | Analog |
5. CSI (Seraj et al. 2015) | 0.18 | 400 | 4Â ns | N/A | N/A | 0.18 | 0.26 | N/A | Analog |
6. CSI (Maymandi-Nejad and Sachdev 2005) | 0.18 | 2 | 320 ps | 0.17–0.34 mW | 5000 μm2 | 13.61 | 36.15 | N/A | Digital |
7. DLL (Chung-Ting et al. 2009) | 0.18 | 70 | 1.57 ns | 2.4–4.2 mW | 0.2584 mm2 | 6.5 | 6 | 3.8 ps | Analog |