Skip to main content

Table 5 Clock and timing results for synchronizer

From: FPGA implemented testbed in 8-by-8 and 2-by-2 OFDM–MIMO channel estimation and design of baseband transceiver

Parameters

Time frequency

Maximum delay of clock net (ns)

2.064

Minimum period (ns)

7.468

Maximum frequency (MHz)

133.905

Maximum path delay from/to any node (ns)

7.468