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Table 3 Clock and timing results for receiver with LS estimation

From: FPGA implemented testbed in 8-by-8 and 2-by-2 OFDM–MIMO channel estimation and design of baseband transceiver

Parameters

Time frequency

Maximum delay of clock net (ns)

2.121

Minimum period (ns)

8.287

Maximum frequency (MHz)

120.671

Maximum path delay from/to any node (ns)

8.287