Skip to main content
Search
Get published
Explore Journals
Books
About
My account
Search all SpringerOpen articles
Search
SpringerPlus
Articles
Table 2
Configurations of target CPU micro architectures used for the experiments
From:
Non-volatile main memory management methods based on a file system
CPU
Intel Atom
Intel Xeon Westmere
Clock
2.13 GHz
3.40 GHz
L1I cache
32 KB
32 KB
L1D cache
24 KB
32 KB
L2 cache
512 KB
256 KB
L3 cache
N/A
8 MB
Back to article page