TY - JOUR AU - Alioto, M. AU - Palumbo, G. PY - 2001 DA - 2001// TI - Power estimation in adiabatic circuits: a simple and accurate model JO - IEEE Trans VLSI Systems VL - 9 UR - https://doi.org/10.1109/92.953495 DO - 10.1109/92.953495 ID - Alioto2001 ER - TY - CHAP AU - Anuar, N. AU - Takahashi, Y. AU - Sekine, T. PY - 2009 DA - 2009// TI - Fundamental logics based on two phase clocked adiabatic static logic BT - Proceedings of 16th IEEE International Conference on Electronics, Circuits and Systems (ICECS 09) PB - Hammarnet CY - Tunisia ID - Anuar2009 ER - TY - JOUR AU - Athas, W. C. AU - Svensson, L. AU - Koller, J. G. AU - Tzartzanis, N. AU - Chou, E. Y. PY - 1994 DA - 1994// TI - Low-power digital systems based on adiabatic-switching principles JO - IEEE Transactions on VLSI Systems VL - 2 UR - https://doi.org/10.1109/92.335009 DO - 10.1109/92.335009 ID - Athas1994 ER - TY - JOUR AU - Benett, C. H. PY - 1998 DA - 1998// TI - Notes on the history of reversible computation JO - IBM J Research and Development VL - 32 UR - https://doi.org/10.1147/rd.321.0016 DO - 10.1147/rd.321.0016 ID - Benett1998 ER - TY - JOUR AU - Bennett, C. H. PY - 1973 DA - 1973// TI - Logical reversibility of computation JO - IBM J Research and Development VL - 17 UR - https://doi.org/10.1147/rd.176.0525 DO - 10.1147/rd.176.0525 ID - Bennett1973 ER - TY - JOUR AU - Dickinson, A. G. AU - Denker, J. S. PY - 1995 DA - 1995// TI - Adiabatic dynamic logic JO - IEEE J Solid-state Circuits VL - 30 UR - https://doi.org/10.1109/4.364447 DO - 10.1109/4.364447 ID - Dickinson1995 ER - TY - JOUR AU - Digantha, S. AU - Sultana, M. AU - Atal, C. PY - 2011 DA - 2011// TI - Realization of a novel reversible SCG gate and its application for designing parallel adder/Subtractor and match logic JO - Int J Computer Applications VL - 31 ID - Digantha2011 ER - TY - JOUR AU - Fischer, J. AU - Amirante, E. AU - Stoffi, A. B. AU - Landsiedel, D. S. PY - 2004 DA - 2004// TI - Improving the positive feedback adiabatic logic family JO - Advances in Radio Science Journal VL - 2 UR - https://doi.org/10.5194/ars-2-221-2004 DO - 10.5194/ars-2-221-2004 ID - Fischer2004 ER - TY - JOUR AU - Haghparast, M. AU - Navi, K. PY - 2008 DA - 2008// TI - Design of a novel fault tolerant reversible full adder for nanotechnology based systems JO - World Applied Sciences Journal VL - 4 ID - Haghparast2008 ER - TY - JOUR AU - Kim, S. AU - Ziesler, C. H. AU - Papaefthymiou, M. C. PY - 2005 DA - 2005// TI - Charge-recovery computing on silicon JO - IEEE Trans Computers VL - 54 UR - https://doi.org/10.1109/TC.2005.91 DO - 10.1109/TC.2005.91 ID - Kim2005 ER - TY - JOUR AU - Landauer, R. PY - 1961 DA - 1961// TI - Irreversibility and heat generation in the computing process JO - IBM J Research and Development VL - 5 UR - https://doi.org/10.1147/rd.53.0183 DO - 10.1147/rd.53.0183 ID - Landauer1961 ER - TY - JOUR AU - Murali, K. V. R. M. AU - Sinha, N. AU - Mahesh, T. S. AU - Levitt, M. H. AU - Ramanathan, K. V. AU - Kumar, A. PY - 2002 DA - 2002// TI - Quantum information processing by Nuclear magnetic resonance:experimental implementation of half-adder and subtractor operations using an oriented spin-7/2 system JO - Physical Review A VL - 66 UR - https://doi.org/10.1103/PhysRevA.66.022313 DO - 10.1103/PhysRevA.66.022313 ID - Murali2002 ER - TY - JOUR AU - Nagamani, A. N. AU - Jayashree, H. V. AU - BhagyaLakshmi, H. R. PY - 2011 DA - 2011// TI - Novel low power comparator design using reversible logic gates JO - Indian J Computer Science and Engineering VL - 2 ID - Nagamani2011 ER - TY - JOUR AU - Noor Muhammed, N. AU - Jamal, N. AU - Hafiz Md, H. B. PY - 2009 DA - 2009// TI - Efficient reversible montgomery multiplier and its application to hardware cryptography JO - Journal of Computer Sciences VL - 5 ID - Noor Muhammed2009 ER - TY - JOUR AU - Peres, A. PY - 1985 DA - 1985// TI - Reversible logic and quantum computers JO - Physical Review A VL - 32 UR - https://doi.org/10.1103/PhysRevA.32.3266 DO - 10.1103/PhysRevA.32.3266 ID - Peres1985 ER - TY - BOOK AU - Perkowski, M. AU - Kerntopf, P. PY - 2001 DA - 2001// TI - Reversible Logic PB - Invited Tutorial Proc CY - EURO-MICRO Warsaw, Poland ID - Perkowski2001 ER - TY - CHAP AU - Perkowski, M. AU - Al-Rabadi, A. AU - Kerntopf, P. AU - Buller, A. AU - Chrzanowska-Jeske, M. AU - Mishchenko, A. AU - Azad Khan, M. AU - Coppola, A. AU - SS, Y. n. AU - Jozwiak, L. PY - 2001 DA - 2001// TI - A general decomposition for reversible logic BT - Proc. Reed Muller Workshop Starkville ID - Perkowski2001 ER - TY - CHAP AU - Siva Kumar, S. H. AU - Shyam, S. AU - Noor Mahammad, S. K. AU - Kamakoti, V. PY - 2006 DA - 2006// TI - Efficient building blocks for reversible sequential circuit design BT - Proceedings of 49th IEEE Int Midwest Symposium on Circuits and Systems (MWSCAS 06) ID - Siva Kumar2006 ER - TY - CHAP AU - Thapliyal, H. AU - Ranganathan, N. PY - 2011 DA - 2011// TI - A new design of the reversible subtractor circuit BT - Proc. of 11th IEEE International Conference on NanoTechnology (IEEE Nano 11) PB - Portland CY - Oregon ID - Thapliyal2011 ER - TY - BOOK AU - Thapliyal, H. AU - Srinivas, M. B. PY - 2005 DA - 2005// TI - Novel reversible TSG gate and its application for designing reversible carry look ahead adder and other adder architectures PB - Proc.of the 10th Asia-Pacific Computer Systems Architecture Conference (ACSAC 05) Lecture Notes of Computer Science CY - Springer-Verlag ID - Thapliyal2005 ER - TY - JOUR AU - Thapliyal, H. AU - Zwolinski, M. PY - 2006 DA - 2006// TI - Reversible logic to cryptographic hardware: In: proceedings of the 49th international midwest symposium on circuits and systems JO - Puerto Rico VL - 1 ID - Thapliyal2006 ER - TY - CHAP AU - Yadav, R. K. AU - Rana, A. K. AU - Chauhan, S. AU - Deepesh, R. AU - Kamalesh, Y. PY - 2011 DA - 2011// TI - Adiabatic Technique for Energy Efficient Logic Circuits Design BT - Proceedings of IEEE International Conference on Emerging Trends in Electrical and Computer Technology (ICERECT 11) ID - Yadav2011 ER -