Name | Direction | Comment |
---|---|---|
Aclr | In | Asynchronous clear input; |
CLK | In | Clock input; |
Ena1 | In | Clock enable input |
DataIn | In | Input data bus; |
Countx[6..0] | In | Counter input bus for X |
County[13..7] | In | Counter input bus for Y |
X[32] | Out | Output of X value; |
Y[32] | Out | Output of Y value; |
W[8] | Out | Output of W value; |